anishathalye / knox
A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities π
β33Updated 3 months ago
Alternatives and similar repositories for knox
Users that are interested in knox are comparing it to the libraries listed below
Sorting:
- A tool for formally verifying constant-time software against hardware π°οΈβ10Updated 3 months ago
- CHERI-RISC-V model written in Sailβ59Updated last month
- Circuits and hardware security modules formally verified with Knox πβ23Updated 3 months ago
- Code repository for Coppelia toolβ23Updated 4 years ago
- Iodine: Verifying Constant-Time Execution of Hardwareβ12Updated 4 years ago
- BTOR2 MLIR projectβ25Updated last year
- work in progress, playing around with btor2 in rustβ11Updated 3 months ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A modelβ80Updated last month
- Verifying OpenTitanβ26Updated last year
- Formal specification and verification of hardware, especially for security and privacy.β126Updated 2 years ago
- Notary: A Device for Secure Transaction Approval πβ28Updated 3 months ago
- Tools for reasoning about circuits in Rosette/Racket πβ19Updated 3 months ago
- The HW-CBMC and EBMC Model Checkers for Verilogβ67Updated this week
- FPGA synthesis tool powered by program synthesisβ46Updated last week
- The source code to the Voss II Hardware Verification Suiteβ56Updated 3 weeks ago
- A Tool for the Static Analysis of Cache Side Channelsβ40Updated 8 years ago
- Symbolic execution tool for Sail ISA specificationsβ66Updated last month
- A repository of tools for verifying constant-timenessβ18Updated 3 months ago
- Testing processors with Random Instruction Generationβ37Updated last month
- PipeProofβ11Updated 5 years ago
- PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Softwareβ39Updated this week
- PyCaliper is Python-based toolingΒ infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,β¦β22Updated 4 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MITβ30Updated this week
- Automatic detection of speculative information flowsβ68Updated 3 years ago
- A core language for rule-based hardware design π¦β153Updated 7 months ago
- Automatically generate a compiler using equality saturationβ29Updated last year
- β19Updated 10 years ago
- Verilog development and verification project for HOL4β26Updated 3 weeks ago
- Pono: A flexible and extensible SMT-based model checkerβ101Updated this week
- A tool for checking the contract satisfaction for hardware designsβ10Updated 5 months ago