Reconfigurable-Computing / Xilinx-FPGA-PCIe-XDMA-TutorialLinks
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
☆26Updated 2 years ago
Alternatives and similar repositories for Xilinx-FPGA-PCIe-XDMA-Tutorial
Users that are interested in Xilinx-FPGA-PCIe-XDMA-Tutorial are comparing it to the libraries listed below
Sorting:
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆51Updated 2 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆140Updated last year
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆79Updated last year
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆113Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆26Updated 2 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆143Updated 2 years ago
- ☆79Updated 3 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆36Updated last year
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。☆88Updated 2 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆34Updated 3 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆97Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆120Updated 2 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆62Updated 6 years ago
- 国产VU13P加速卡资料☆79Updated 8 months ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆154Updated last year
- ARM中通过APB总线连接的UART模块☆69Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- ☆65Updated 3 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- ☆38Updated 10 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- An AXI DDR3 SDRAM controller for FPGA☆41Updated last year
- Implementation of the PCIe physical layer☆57Updated 4 months ago