An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
☆47May 20, 2021Updated 4 years ago
Alternatives and similar repositories for FPGA_ADC
Users that are interested in FPGA_ADC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆73Sep 14, 2021Updated 4 years ago
- Contains source code for sin/cos table verification using UVM☆21Mar 9, 2021Updated 5 years ago
- Sigma-Delta Analog to Digital Converter in FPGA (VHDL)☆15Dec 19, 2017Updated 8 years ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆22Jun 26, 2023Updated 2 years ago
- Simple pin assignment generator for IC case☆19Feb 14, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆36Aug 19, 2020Updated 5 years ago
- Implementation of tappped delay line TDC on FPGA☆15Dec 28, 2022Updated 3 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Apr 5, 2024Updated 2 years ago
- SERDES-based TDC core for Spartan-6☆19Aug 2, 2012Updated 13 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆74Jun 16, 2022Updated 3 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆32Mar 13, 2025Updated last year
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Wireless training timer for BMX, cycling, sprint, speed slalom and other athletics. Based on ESP8266.☆17Nov 25, 2025Updated 5 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆16Aug 24, 2024Updated last year
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24May 8, 2020Updated 5 years ago
- ☆13Oct 30, 2025Updated 6 months ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Jan 13, 2025Updated last year
- FPGA for uSDR☆21Apr 18, 2026Updated 2 weeks ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆63Jan 12, 2021Updated 5 years ago
- A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.☆24Jul 15, 2017Updated 8 years ago
- ☆16Jan 9, 2022Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆60Dec 31, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…☆28Feb 7, 2023Updated 3 years ago
- A configurable C++ generator of pipelined Verilog FFT cores☆257Apr 18, 2024Updated 2 years ago
- Fault Injection Automatic Test Equipment☆15Nov 22, 2021Updated 4 years ago
- The Reconfigurable Solver for QP☆11Apr 19, 2023Updated 3 years ago
- Open source Photonics PDK for VTT's 3 um SOI platform.☆14Updated this week
- Time to Digital Converter (TDC)☆36Dec 27, 2020Updated 5 years ago
- Saturn SDR Radio: Xilinx FPGA and Raspberry Pi 4 CM☆48Updated this week
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆129Feb 11, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆12Jul 20, 2022Updated 3 years ago
- Open FPGA Modules☆24Oct 8, 2024Updated last year
- FPGA based 30ps RMS TDCs☆92Mar 18, 2018Updated 8 years ago
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Apr 9, 2026Updated 3 weeks ago
- ☆33Apr 30, 2023Updated 3 years ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 3 years ago
- 在嵌入式软件开发当中，常常第一步就是设计整个系统的架构。有基于OS的，也有裸机的。我们先拿裸机说事儿，我想很多人在做单片机的裸机开发（甚至基于OS）时脑海里根 本没有设计架构的想法，从来都是while（1）循环到底，能写点状态机已经算是基础扎实的人物了。那么问题来了，whil…☆13Nov 25, 2019Updated 6 years ago