LukiLeu / FPGA_ADC
An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
☆45Updated 3 years ago
Alternatives and similar repositories for FPGA_ADC:
Users that are interested in FPGA_ADC are comparing it to the libraries listed below
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆63Updated 3 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- ☆41Updated last year
- Extensible FPGA control platform☆60Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 2 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- JESD204b modules in VHDL☆30Updated 6 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆43Updated 3 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆85Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- I2C Master Verilog module☆33Updated this week
- An open-source HDL register code generator fast enough to run in real time.☆64Updated last week
- ☆30Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆62Updated 2 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆35Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆53Updated 4 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- IEEE P1735 decryptor for VHDL☆31Updated 9 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆69Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆57Updated this week
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆59Updated 3 years ago
- All digital PLL☆28Updated 7 years ago
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆96Updated 8 years ago
- ☆33Updated 2 years ago
- UART -> AXI Bridge☆61Updated 3 years ago