UofT-HPRC / galapagosView external linksLinks
☆15Jun 24, 2025Updated 7 months ago
Alternatives and similar repositories for galapagos
Users that are interested in galapagos are comparing it to the libraries listed below
Sorting:
- ☆18Jan 22, 2025Updated last year
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16May 26, 2021Updated 4 years ago
- A fully open source low cost FPGA board for makers , hobbyist and student for endless possibility.☆37Dec 13, 2025Updated 2 months ago
- ☆19Aug 9, 2022Updated 3 years ago
- ☆25May 9, 2019Updated 6 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Apr 5, 2024Updated last year
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆43Oct 13, 2023Updated 2 years ago
- Collection of hardware description languages writings and code snippets☆28Jan 29, 2015Updated 11 years ago
- DASS HLS Compiler☆29Oct 4, 2023Updated 2 years ago
- Fixed point package for Python.☆36Apr 28, 2023Updated 2 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- SAMO: Streaming Architecture Mapping Optimisation☆34Oct 4, 2023Updated 2 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- ☆21Nov 12, 2025Updated 3 months ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆40Feb 24, 2025Updated 11 months ago
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- ☆13Jan 22, 2026Updated 3 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆57Updated this week
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆43Feb 5, 2026Updated last week
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated last year
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- ☆10Nov 5, 2019Updated 6 years ago
- Design of High-Level Synthesis of Xilinx FFT IP core via FFT library☆13Jul 17, 2023Updated 2 years ago
- NeuraLUT-Assemble☆47Aug 20, 2025Updated 5 months ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- Time management library for embedded devices☆12Apr 21, 2019Updated 6 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- ☆10Oct 18, 2024Updated last year
- mechatronics firmware☆13Apr 14, 2025Updated 10 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Code repository for my articles on blogs.embarcadero.com and pythongui.org.☆13Feb 6, 2025Updated last year
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 6 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- ☆20May 8, 2012Updated 13 years ago
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆15Nov 18, 2025Updated 2 months ago
- VHDL sources for a BT.656 to axi4-stream converter☆11Mar 20, 2023Updated 2 years ago