UofT-HPRC / galapagos

Related projects ⓘ

Alternatives and complementary repositories for galapagos

• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆24Updated 4 years ago
• Kareem-Emad / DCNN-Accelerator
  Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.
  ☆12Updated 5 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 3 years ago
• zslwyuan / Zynq_HLS_DDR_Dataflow_kernel_2mm
  This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…
  ☆19Updated 5 years ago
• chipsalliance / aib-protocols
  ☆24Updated 9 months ago
• kmanev / ZynqUSp-AXI-Speedtest
  ☆13Updated 4 years ago
• pgroupATusc / GraphACT
  Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".
  ☆10Updated 4 years ago
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆16Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆22Updated 5 years ago
• asadalam / FINN_MatrixVector_RTL
  Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…
  ☆15Updated 2 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆27Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆39Updated 4 years ago
• dac-sdc / fpga_starter_2023
  ☆8Updated last year
• UIUC-ChenLab / rip
  ☆17Updated 6 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆43Updated last year
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆3Updated 3 years ago
• xupgit / compute_acceleration
  ☆12Updated 4 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆30Updated this week
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆19Updated this week
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆22Updated 3 months ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆56Updated 4 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆23Updated 5 months ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆30Updated last year
• awai54st / Logic-Shrinkage
  ☆20Updated 2 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆67Updated 10 years ago
• Xilinx / pcie_qdma_ats_example
  ☆22Updated 3 years ago
• UCLA-VAST / hbmbench
  ☆23Updated 3 years ago
• icgrp / prflow_nested_dfx
  Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
  ☆12Updated 8 months ago
• gilani / fpfma
  Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
  ☆17Updated 11 years ago