Alternatives and similar repositories for RISC-V-All-Aboard-zh-cn

Users that are interested in RISC-V-All-Aboard-zh-cn are comparing it to the libraries listed below

• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆30Updated 5 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆43Updated last year
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆24Updated this week
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• Nuclei-Software / nuclei-ai-library
  Nuclei AI Library Optimized For RISC-V Vector
  ☆13Updated last week
• zetalog / sdfirm
  Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.
  ☆20Updated 2 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆20Updated 5 months ago
• ansonn / esl_systemc
  systemc建模相关
  ☆27Updated 11 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆67Updated last month
• Nuclei-Software / e603_hbird
  RV64GC Linux Capable RISC-V Core
  ☆40Updated last month
• compiler-dev / llvm-rv
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆43Updated 4 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆16Updated last year
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆13Updated last year
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 2 years ago
• horie-t / homemade-riscv-en
  Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"
  ☆17Updated 6 years ago
• plctlab / plct-qemu
  PLCT实验室维护的QEMU仓库。代码放在 plct- 前缀的分支里。
  ☆28Updated last month
• TYOD-SOC / RISCV-Accelerator
  ☆37Updated 6 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆45Updated 8 months ago
• xjtuiair-cag / SiYuan
  A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
  ☆30Updated last week
• msyksphinz-self / minimal-diplomacy
  Example of Chisel3 Diplomacy
  ☆11Updated 3 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆68Updated 3 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆53Updated 3 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆42Updated last year
• lingscale / cc01
  ☆30Updated 7 months ago
• yu-yake2002 / ysyx-docker
  A docker image for One Student One Chip's debug exam
  ☆11Updated 2 years ago
• AlSaqr-platform / he-soc
  ☆32Updated last week
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago