sangjae4309 / gem5-ramulator2Links
This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials and configuration, you can run simulations in gem5 backed by the detailed timing and behavior modeling of Ramulator2.
☆12Updated 4 months ago
Alternatives and similar repositories for gem5-ramulator2
Users that are interested in gem5-ramulator2 are comparing it to the libraries listed below
Sorting:
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆71Updated last year
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- ☆11Updated 2 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆39Updated 2 months ago
- A list of our chiplet simulaters☆42Updated 3 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib …☆18Updated 6 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆81Updated 3 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆65Updated 10 months ago
- ☆36Updated 6 months ago
- ☆59Updated 6 months ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆53Updated 2 months ago
- ☆17Updated 6 months ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆67Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆67Updated 2 weeks ago
- ☆45Updated 4 months ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆11Updated 6 years ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆24Updated 10 months ago
- An integrated CGRA design framework☆91Updated 7 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆65Updated 3 weeks ago
- ☆48Updated 2 months ago
- Processing in Memory Emulation☆22Updated 2 years ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆36Updated 10 months ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Updated 4 years ago
- ☆25Updated 2 years ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆23Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆39Updated 2 years ago
- ☆32Updated 11 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆70Updated 5 months ago
- gem5 repository to study chiplet-based systems☆81Updated 6 years ago