scale-snu / attacc_simulatorLinks
☆92Updated last year
Alternatives and similar repositories for attacc_simulator
Users that are interested in attacc_simulator are comparing it to the libraries listed below
Sorting:
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆94Updated last year
- Processing-In-Memory (PIM) Simulator☆194Updated 9 months ago
- ☆151Updated 8 months ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆92Updated 5 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆93Updated 5 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆47Updated last year
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆38Updated 2 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆75Updated 6 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆65Updated 5 months ago
- ☆47Updated last month
- UPMEM LLM Framework allows profiling PyTorch layers and functions and simulate those layers/functions with a given hardware profile.☆35Updated 2 months ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆42Updated last month
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆64Updated 9 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆150Updated 7 months ago
- A co-design architecture on sparse attention☆52Updated 4 years ago
- ☆189Updated last year
- ☆18Updated 2 years ago
- ☆44Updated 4 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- PIMeval simulator and PIMbench suite☆34Updated 2 months ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆67Updated 2 years ago
- ☆48Updated 4 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆66Updated last week
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆36Updated 9 months ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆86Updated last year
- STONNE: A Simulation Tool for Neural Networks Engines☆139Updated 3 months ago
- PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training☆18Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆38Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆70Updated last year
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Updated 4 years ago