scale-snu / attacc_simulator
☆48Updated 6 months ago
Alternatives and similar repositories for attacc_simulator:
Users that are interested in attacc_simulator are comparing it to the libraries listed below
- NeuPIMs Simulator☆65Updated 6 months ago
- ☆17Updated last year
- Processing-In-Memory (PIM) Simulator☆145Updated last month
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆44Updated last month
- UPMEM LLM Framework allows profiling PyTorch layers and functions and simulate those layers/functions with a given hardware profile.☆16Updated last month
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆83Updated last month
- ☆112Updated 2 weeks ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆65Updated 4 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆58Updated this week
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆51Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-Optimization☆27Updated 10 months ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆31Updated last year
- ☆104Updated 6 months ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆21Updated last month
- A co-design architecture on sparse attention☆48Updated 3 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆25Updated 7 months ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆61Updated last year
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆81Updated 8 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆77Updated last year
- PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training☆15Updated 7 months ago
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆8Updated this week
- ☆21Updated last month
- ☆62Updated 3 years ago
- RTL implementation of Flex-DPE.☆97Updated 4 years ago
- A Cycle-level simulator for M2NDP☆21Updated last month
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆46Updated this week
- ☆19Updated last month
- STONNE: A Simulation Tool for Neural Networks Engines☆123Updated 7 months ago
- ☆25Updated 3 years ago