Alternatives and similar repositories for A-Primer-on-Memory-Consistency-and-Cache-Coherence

Users that are interested in A-Primer-on-Memory-Consistency-and-Cache-Coherence are comparing it to the libraries listed below

• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆171Updated 8 months ago
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆578Updated 10 months ago
• DawnCarol / DawnCarol
  ☆194Updated 2 months ago
• weedge / perf-book-cn
  https://github.com/dendibakh/perf-book gitbook在线电子书，翻译成中文原始markdown文档
  ☆91Updated 5 months ago
• OpenXiangShan / NEMU
  ☆280Updated last week
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆41Updated 2 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆281Updated last week
• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆222Updated 3 years ago
• runninglinuxkernel / riscv_programming_practice
  ☆209Updated last year
• sunshaoce / rvcc-course
  ☆89Updated last year
• sunshaoce / rvcc
  本课程基于Rui的chibicc，@sunshaoce和@ksco将其由原来的X86架构改写为RISC-V 64架构，同时加入了大量的中文注释，并且配有316节对应于每一个commit的课程，帮助读者可以层层推进、逐步深入的学习编译器的构造。
  ☆351Updated 2 years ago
• P2Tree / LLVM_for_cpu0
  This is a tutorial to learn LLVM, I realize a backend to compiler machine code for cpu0 which is a simple RISC cpu.
  ☆248Updated 3 years ago
• JamesAslan / MicroArchBench
  ☆73Updated 7 months ago
• Shuiliusheng / boom_stop
  jump to a place when progam runs to the max instruction number
  ☆12Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆754Updated this week
• OSCPU / NutShell-doc
  ☆122Updated 2 years ago
• OSCPU / ysyx-workbench
  ☆151Updated 3 weeks ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆146Updated 2 years ago
• NJU-ProjectN / fceux-am
  ☆97Updated 7 months ago
• OpenXiangShan / GEM5
  ☆86Updated this week
• ISRC-CAS / riscv-isa-manual-cn
  ☆175Updated last year
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆417Updated last week
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆17Updated 6 years ago
• plctlab / llvm-project
  PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
  ☆160Updated 6 months ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆172Updated 3 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆159Updated 5 months ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆64Updated last year
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆131Updated last year
• iiicp / study-llvm-from-scratch
  llvm slides and books and other
  ☆46Updated 4 months ago