A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划
☆373May 5, 2024Updated 2 years ago
Alternatives and similar repositories for A-Primer-on-Memory-Consistency-and-Cache-Coherence
Users that are interested in A-Primer-on-Memory-Consistency-and-Cache-Coherence are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 体系结构研讨 + ysyx高阶大纲 (WIP☆217Oct 14, 2024Updated last year
- ☆247Jun 25, 2025Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆43Updated this week
- Collect some IC specs for learning.☆25Jun 25, 2024Updated 2 years ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆668Aug 13, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Collect some IC textbooks for learning.☆228Aug 11, 2022Updated 4 years ago
- ☆14Mar 19, 2025Updated last year
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- RISC-V SIMD Superscalar Dual-Issue Processor☆31Apr 24, 2025Updated last year
- ☆80Updated this week
- Documentation for XiangShan Design☆51Updated this week
- The official NaplesPU hardware code repository☆36Jul 27, 2019Updated 7 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆940Aug 18, 2026Updated 2 weeks ago
- 自建 chisel 工程模板☆15Jul 19, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆52Mar 31, 2026Updated 5 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆26Jan 21, 2026Updated 7 months ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- ☆83Oct 29, 2024Updated last year
- ☆13Nov 5, 2017Updated 8 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆398Aug 19, 2026Updated last week
- Open-source non-blocking L2 cache☆65Updated this week
- The Source Code Lib for BiscuitOS☆12Oct 15, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- ☆61Aug 30, 2021Updated 5 years ago
- ☆42Oct 12, 2025Updated 10 months ago
- ☆101Apr 2, 2025Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Updated this week
- PCI Express controller model☆80Oct 5, 2022Updated 3 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated last month
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- a training-target implementation of rv32im, designed to be simple and easy to understand☆60Dec 27, 2021Updated 4 years ago
- ☆277Aug 25, 2026Updated last week
- CUDA PTX-ISA Document 中文翻译版☆58Sep 29, 2025Updated 11 months ago
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 6 months ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆18Sep 29, 2024Updated last year
- "aura" my super-scalar O3 cpu core☆26May 25, 2024Updated 2 years ago
- USTC 体系结构 资料☆15Jul 17, 2022Updated 4 years ago