Alternatives and similar repositories for JSON-for-VHDL

Users that are interested in JSON-for-VHDL are comparing it to the libraries listed below

• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆50Updated 3 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆150Updated last week
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆58Updated last month
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆72Updated last week
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆115Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 4 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 10 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆70Updated 2 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆58Updated 3 weeks ago
• pieter3d / simview
  ☆88Updated 2 months ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆73Updated 3 weeks ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆82Updated 3 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆43Updated last month
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆83Updated 5 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• VHDL / news
  VHDL related news.
  ☆27Updated this week
• OSVVM / Documentation
  OSVVM Documentation
  ☆36Updated this week
• kevinpt / symbolator
  HDL symbol generator
  ☆197Updated 2 years ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆156Updated last week