Alternatives and similar repositories for JSON-for-VHDL

Users that are interested in JSON-for-VHDL are comparing it to the libraries listed below

• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆139Updated last week
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆58Updated 4 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆65Updated 2 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆61Updated last week
• OSVVM / Documentation
  OSVVM Documentation
  ☆34Updated 3 weeks ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated 2 weeks ago
• pieter3d / simview
  ☆79Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆137Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆59Updated 3 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆52Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆67Updated 8 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆219Updated 2 weeks ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆113Updated 8 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆43Updated 4 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆69Updated 3 years ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 6 months ago
• wifasoi / WaveDromTikZ
  An implementation of WaveDrom which outputs TikZ for use in LaTeX documents.
  ☆44Updated 3 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆83Updated 3 weeks ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated 7 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated 10 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year