Paebbels / JSON-for-VHDL

Related projects ⓘ

Alternatives and complementary repositories for JSON-for-VHDL

• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆62Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆46Updated this week
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 2 weeks ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆53Updated 4 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆105Updated 2 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• pieter3d / simview
  ☆76Updated 8 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆51Updated last month
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆52Updated last week
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 3 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆202Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆64Updated 2 months ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆55Updated this week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆81Updated 4 months ago
• slaclab / ruckus
  Vivado build system
  ☆71Updated this week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆81Updated 6 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆30Updated last month
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆169Updated 10 months ago
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆52Updated 2 months ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆107Updated last month
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• chipsalliance / UHDM-integration-tests
  ☆30Updated last year
• kevinpt / symbolator
  HDL symbol generator
  ☆185Updated last year
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆50Updated last month
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆32Updated last month
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆76Updated 4 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆138Updated 3 weeks ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆47Updated 2 months ago
• FPGA-Research-Manchester / FABulous
  Fabric generator and CAD tools
  ☆148Updated last week