abs-tudelft / vhdre
Generator for VHDL regular expression matchers
☆14Updated 4 years ago
Alternatives and similar repositories for vhdre:
Users that are interested in vhdre are comparing it to the libraries listed below
- VHDL dependency analyzer☆23Updated 5 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆12Updated 2 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 3 years ago
- VHDL plugin for RgGen☆12Updated 2 months ago
- VHDL String Formatting Library☆25Updated 11 months ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Updated last year
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆30Updated 2 months ago
- VHDL related news.☆25Updated this week
- Example of Test Driven Design with VUnit☆14Updated 3 years ago
- IP Core Library - Published and maintained by the Open Source VHDL Group☆10Updated 2 weeks ago
- VHDL package to provide C-like string formatting☆15Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- Library of reusable VHDL components☆28Updated last year
- Interfacing VHDL and foreign languages with VUnit☆14Updated 5 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated 9 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- TCL framework to package Vivado IP-Cores☆15Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last month
- ☆33Updated last year
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Updated last year
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Updated 4 years ago
- ☆20Updated 4 years ago
- A flexible and scalable development platform for modern FPGA projects.☆23Updated 2 weeks ago
- A VHDL Core Library.☆17Updated 8 years ago
- Python/Simulator integration using procedure calls☆9Updated 5 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- Interface definitions for VHDL-2019.☆12Updated last year