abs-tudelft / vhdre

Related projects ⓘ

Alternatives and complementary repositories for vhdre

• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆22Updated 4 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆16Updated 7 months ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆23Updated 6 months ago
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆11Updated this week
• TerosTechnology / teroshdl-documenter-demo
  This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…
  ☆10Updated 2 years ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆29Updated this week
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 2 years ago
• NJDFan / register-maps
  Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.
  ☆12Updated 2 years ago
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆14Updated 3 years ago
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated last year
• VHDL / news
  VHDL related news.
  ☆24Updated this week
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 8 months ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 4 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 3 years ago
• paulscherrerinstitute / PsiIpPackage
  TCL framework to package Vivado IP-Cores
  ☆14Updated 2 years ago
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 2 years ago
• VHDL / CoreLib
  A VHDL Core Library.
  ☆17Updated 7 years ago
• drom / sta
  🕒 Static Timing Analysis diagram renderer
  ☆12Updated 11 months ago
• wzab / agwb
  Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems
  ☆12Updated 11 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆21Updated 6 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆25Updated 8 months ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆22Updated 4 months ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• eine / hwd-ide
  ☆19Updated 4 years ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆15Updated 2 weeks ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆18Updated 3 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆37Updated this week
• edaa-org / pyEDAA.IPXACT
  An IP-XACT DOM for IEEE 1685-2014 in Python.
  ☆19Updated last week
• suoto / fpga_cores
  ☆32Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆30Updated 2 months ago