Alternatives and similar repositories for fpga_cores:

Users that are interested in fpga_cores are comparing it to the libraries listed below

• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆33Updated 10 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆46Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 3 weeks ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆44Updated this week
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆14Updated 3 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆52Updated 4 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 5 months ago
• VHDL / news
  VHDL related news.
  ☆25Updated this week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 2 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated last week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆57Updated last year
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆22Updated 7 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated 2 weeks ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated this week
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• wallento / cocotbext-wishbone
  ☆13Updated 2 months ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• schang412 / cocotbext-spi
  ☆20Updated 3 months ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆18Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 4 years ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 5 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 3 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆27Updated 11 months ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 2 years ago
• rodrigomelo9 / FOSS-for-FPGAs
  A getting started presentation (with examples) about how to use FLOSS for FPGA development.
  ☆35Updated last year