tmeissner / cryptocores

Related projects ⓘ

Alternatives and complementary repositories for cryptocores

• suoto / fpga_cores
  ☆32Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆30Updated 2 months ago
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated last year
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 4 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 8 months ago
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆14Updated 3 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆22Updated this week
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆40Updated 10 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆25Updated 8 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆23Updated last week
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆16Updated 7 months ago
• schang412 / cocotbext-spi
  ☆20Updated 3 weeks ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 2 years ago
• VHDL / news
  VHDL related news.
  ☆24Updated this week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆37Updated this week
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆20Updated last year
• TerosTechnology / teroshdl-documenter-demo
  This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…
  ☆10Updated 2 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆18Updated 3 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆43Updated 11 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆24Updated 4 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆47Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆64Updated 2 months ago
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆11Updated this week
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆22Updated 4 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆41Updated 2 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆23Updated 6 months ago