aoeldemann / cocotb
cocotb code library
☆13Updated 4 years ago
Alternatives and similar repositories for cocotb:
Users that are interested in cocotb are comparing it to the libraries listed below
- ideas and eda software for vlsi design☆50Updated last week
- Generate address space documentation HTML from compiled SystemRDL input☆51Updated 2 weeks ago
- ☆26Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆59Updated 3 weeks ago
- ☆10Updated 6 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- ☆31Updated last year
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆64Updated last week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆24Updated 2 months ago
- Running Python code in SystemVerilog☆68Updated 9 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 8 months ago
- Import and export IP-XACT XML register models☆34Updated 6 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Updated 3 weeks ago
- Python script to transform a VCD file to wavedrom format☆76Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- SystemVerilog Linter based on pyslang☆30Updated last week
- Python interface for cross-calling with HDL☆32Updated last month
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 4 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- ☆13Updated 4 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆59Updated 3 years ago
- ☆20Updated this week