Alternatives and similar repositories for xpm_vhdl

Users that are interested in xpm_vhdl are comparing it to the libraries listed below

• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 9 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆63Updated 4 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated last week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• wallento / cocotbext-wishbone
  ☆18Updated 11 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆76Updated 2 weeks ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated 2 months ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 4 months ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆41Updated this week
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆41Updated last month
• VHDL / news
  VHDL related news.
  ☆26Updated this week
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 3 weeks ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated 3 weeks ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆40Updated last month
• schang412 / cocotbext-spi
  ☆27Updated 7 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated last month
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆70Updated this week
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆51Updated last year
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆152Updated this week
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆31Updated 2 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆67Updated last month
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆70Updated last month
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆16Updated 3 years ago