GitHub-based statistics highlighting interesting facts about the HDL industry
☆12Jul 6, 2023Updated 3 years ago
Alternatives and similar repositories for github-facts
Users that are interested in github-facts are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VHDL related news.☆27Updated this week
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- VUnit GitHub action☆19May 23, 2021Updated 5 years ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- ☆20May 5, 2020Updated 6 years ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 9 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- A simple Emacs minor mode for VUnit☆12Jul 14, 2025Updated last year
- ☆33Jul 15, 2026Updated 3 weeks ago
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆17Apr 10, 2025Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆53Updated this week
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Mar 12, 2026Updated 4 months ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆70Jul 29, 2026Updated last week
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- A first approach of getting a pure Ada program running on an FPGA with SaxonSOC☆10Apr 12, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 10 months ago
- GHDL C extensions☆12Feb 20, 2020Updated 6 years ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 3 years ago
- A JSON library implemented in VHDL.☆85Jul 13, 2026Updated 3 weeks ago
- Standard and Curated cores, tested and working.☆11Dec 29, 2022Updated 3 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated 2 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- Dockerfile with Vivado for CI☆12Apr 27, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 4 years ago
- VHDL plugin for RgGen☆15Jul 1, 2026Updated last month
- PNG encoder, implemented in VHDL☆23Mar 30, 2024Updated 2 years ago
- Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board☆15Nov 16, 2022Updated 3 years ago
- Network protocol libraries for VHDL test benches☆13Mar 9, 2026Updated 5 months ago
- A getting started presentation (with examples) about how to use FLOSS for FPGA development.☆37Sep 18, 2023Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆123Oct 3, 2024Updated last year