Alternatives and similar repositories for yosys-ice-experiments

Users that are interested in yosys-ice-experiments are comparing it to the libraries listed below

• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• mcmayer / iCE40
  Lattice iCE40 FPGA experiments - Work in progress
  ☆105Updated 3 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆67Updated 3 years ago
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆24Updated 7 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 6 years ago
• knielsen / ice40_viewer
  ☆59Updated last year
• forflo / yodl
  A VHDL frontend for Yosys
  ☆102Updated 8 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 7 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• cyrozap / iCEstick-UART-Demo
  This is a simple UART echo test for the iCEstick Evaluation Kit
  ☆38Updated 6 years ago
• makestuff / libfpgalink
  LIB:Library for interacting with an FPGA over USB
  ☆84Updated 4 years ago
• lawrie / tiny_usb_examples
  Using the TinyFPGA BX USB code in user designs
  ☆50Updated 6 years ago
• ObKo / USBCore
  USB Full-Speed/Hi-Speed Device Controller core for FPGA
  ☆32Updated 4 years ago
• blackmesalabs / sump2
  open-source logic analyzer for FPGAs
  ☆96Updated 6 years ago
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆54Updated 2 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆86Updated 6 years ago
• pliu6 / vhd2vl
  vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
  ☆26Updated 9 years ago
• freecores / freecores.github.io
  Freecores website
  ☆19Updated 8 years ago
• GuzTech / ulx3s-nmigen-examples
  nMigen examples for the ULX3S board
  ☆16Updated 4 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆49Updated 6 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• abnoname / iceZ0mb1e
  FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
  ☆57Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week
• hedgeberg / VerilogCommon
  A repo of basic Verilog/SystemVerilog modules useful in other circuits.
  ☆21Updated 7 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• JohnDMcMaster / project2064
  XC2064 bitstream documentation
  ☆16Updated 6 years ago
• alvieboy / ZPUino-HDL
  ZPUino HDL implementation
  ☆90Updated 6 years ago