A VHDL Core Library.
☆18Mar 29, 2017Updated 9 years ago
Alternatives and similar repositories for CoreLib
Users that are interested in CoreLib are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 6 years ago
- VHDL related news.☆27Updated this week
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated last year
- VHDLproc is a VHDL preprocessor☆25May 12, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A JSON library implemented in VHDL.☆87Jul 13, 2026Updated 3 months ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- Interface definitions for VHDL-2019.☆36May 13, 2026Updated 5 months ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- A Sphinx domain providing VHDL language support.☆21Updated this week
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…☆16Oct 4, 2026Updated 3 weeks ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- Streaming based VHDL parser.☆86Updated this week
- OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation☆15Oct 21, 2026Updated last week
- Generate verilog register file from systemRDL description☆14Feb 9, 2024Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 4 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆70Feb 16, 2026Updated 8 months ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.