HunterBitos / Implementation-of-AMBA-AXI3-protocolLinks
Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System Verilog simulator and the Mentor Graphics Veloce hardware emulator.
☆12Updated 8 years ago
Alternatives and similar repositories for Implementation-of-AMBA-AXI3-protocol
Users that are interested in Implementation-of-AMBA-AXI3-protocol are comparing it to the libraries listed below
Sorting:
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆36Updated 2 years ago
- Verification IP for APB protocol☆71Updated 4 years ago
- ☆37Updated 4 months ago
- Simple single-port AXI memory interface☆46Updated last year
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆37Updated 5 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆17Updated 4 years ago
- General Purpose AXI Direct Memory Access☆60Updated last year
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- System Verilog using Functional Verification☆12Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆73Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- SystemVerilog UVM testbench example☆35Updated last year
- Sample UVM code for axi ram dut☆37Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- SoC Based on ARM Cortex-M3☆33Updated 5 months ago
- ☆26Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- ☆49Updated 4 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- AXI Interconnect☆53Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- SystemVerilog VIP for AMBA APB protocol☆79Updated 3 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated 4 months ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆36Updated last year
- UART design in SV and verification using UVM and SV☆49Updated 5 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated 2 years ago