HunterBitos / Implementation-of-AMBA-AXI3-protocol
Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System Verilog simulator and the Mentor Graphics Veloce hardware emulator.
☆12Updated 7 years ago
Alternatives and similar repositories for Implementation-of-AMBA-AXI3-protocol:
Users that are interested in Implementation-of-AMBA-AXI3-protocol are comparing it to the libraries listed below
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 6 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- SystemVerilog examples and projects☆17Updated 6 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆32Updated 2 years ago
- Maven Silicon Project☆17Updated 6 years ago
- ☆27Updated 10 months ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆15Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- AXI4 BFM in Verilog☆31Updated 8 years ago
- CORE-V MCU UVM Environment and Test Bench☆18Updated 7 months ago
- Verification IP for APB protocol☆57Updated 4 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- ☆16Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- ☆23Updated 11 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- System on Chip verified with UVM/OSVVM/FV☆23Updated last month
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆29Updated 4 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- SoC Based on ARM Cortex-M3☆27Updated last month