Alternatives and similar repositories for FPGA_TDC_1_0

Users that are interested in FPGA_TDC_1_0 are comparing it to the libraries listed below

• shinde-shantanu / FPGA_TDC
  Time to Digital Converter on an FPGA
  ☆14Updated 4 years ago
• PranavGovekar / tdcOnFPGA
  Implementation of tappped delay line TDC on FPGA
  ☆12Updated 2 years ago
• gonzagab / tdc
  A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.
  ☆21Updated 7 years ago
• RuiMachado39 / TDC
  Verilog implementation of a tapped delay line TDC
  ☆39Updated 6 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆61Updated 3 years ago
• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆60Updated 10 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• marsohod4you / FpgaTDC
  Project: Precise Measure of time delays in FPGA
  ☆30Updated 7 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆49Updated 2 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆32Updated 4 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆17Updated 6 years ago
• vladniculescu / High-Speed-FPGA-based-Data-Acquisition-System-100MSPS
  ☆18Updated last year
• benbr8 / tdc-fpga
  A Time to Digital Converter designed for Xilinx 7-Series FPGAs
  ☆27Updated 4 years ago
• jobisoft / jTDC
  FPGA based 30ps RMS TDCs
  ☆84Updated 7 years ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆46Updated 3 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆36Updated 3 years ago
• samsamfire / Kalman_Fpga
  Fixed Point Kalman filter for fpga
  ☆20Updated 5 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆54Updated 3 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆45Updated last month
• charkster / spi_slave_verilog
  SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
  ☆15Updated 5 years ago
• natanvotre / fm-transmitter
  FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic …
  ☆15Updated 4 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆70Updated 2 years ago
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆23Updated 5 years ago
• DeamonYang / FPGA_USB2.0_DAQ
  基于USB2.0 的数据采集卡
  ☆19Updated 6 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆32Updated 2 years ago
• filipamator / adpll
  All digital PLL
  ☆28Updated 7 years ago
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆66Updated 3 years ago
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆28Updated 2 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆31Updated 5 years ago