LGG1997 / FPGA_TDC_1_0
☆10Updated 2 years ago
Alternatives and similar repositories for FPGA_TDC_1_0:
Users that are interested in FPGA_TDC_1_0 are comparing it to the libraries listed below
- Time to Digital Converter on an FPGA☆14Updated 4 years ago
- Implementation of tappped delay line TDC on FPGA☆13Updated 2 years ago
- Verilog implementation of a tapped delay line TDC☆38Updated 6 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆55Updated 3 years ago
- A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.☆20Updated 7 years ago
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆59Updated 9 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆30Updated 4 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- Project: Precise Measure of time delays in FPGA☆28Updated 7 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆47Updated 2 years ago
- FPGA based 30ps RMS TDCs☆82Updated 6 years ago
- Fixed Point Kalman filter for fpga☆16Updated 4 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer