The CORDIC algorithm implemented in Octave/MATLAB and Verilog
☆32Mar 31, 2015Updated 10 years ago
Alternatives and similar repositories for CORDIC
Users that are interested in CORDIC are comparing it to the libraries listed below
Sorting:
- configurable cordic core in verilog☆53Jul 17, 2014Updated 11 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- Implementation of CORDIC Algorithms Using Verilog☆24Apr 26, 2021Updated 4 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC☆14Jul 15, 2016Updated 9 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- SPI Master Core clone from OpenCores☆12Oct 4, 2013Updated 12 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- An implementation of the CORDIC algorithm in Verilog.☆109Nov 19, 2018Updated 7 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 6 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆35Sep 6, 2018Updated 7 years ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆26Mar 13, 2025Updated 11 months ago
- A CIC filter implemented in Verilog☆25Sep 7, 2015Updated 10 years ago
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Aug 10, 2022Updated 3 years ago
- QSPI for SoC☆23Nov 8, 2019Updated 6 years ago
- FIR filter implementation☆29Mar 19, 2020Updated 5 years ago
- Mathematical Functions in Verilog☆97Mar 7, 2021Updated 4 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆34Updated this week
- Systemverilog DPI-C call Python function☆27Mar 11, 2021Updated 4 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆28Mar 26, 2017Updated 8 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated last month
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆32May 6, 2017Updated 8 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 2 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆33Aug 7, 2021Updated 4 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 12 years ago
- Robotics Learning Note☆11Jun 22, 2018Updated 7 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- Hardware and software of Taiji-Uino DUE(Arduino DUE compitable board)☆11Mar 3, 2015Updated 11 years ago
- FIR band-pass filter using Verilog HDL.☆12Sep 6, 2020Updated 5 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago