FPGA-based SATA-DMA Host Controller
☆36Nov 20, 2025Updated 10 months ago
Alternatives and similar repositories for AFXSATA
Users that are interested in AFXSATA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 8 years ago
- ☆38Mar 10, 2021Updated 5 years ago
- Joker TV (USB) FPGA verilog/vhdl code☆16May 19, 2026Updated 4 months ago
- A project demonstrate how to config ad9361 to TX mode☆13Dec 9, 2018Updated 7 years ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。☆147Sep 14, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆43Jul 4, 2026Updated 3 months ago
- 国产VU13P加速卡资料☆86Mar 17, 2025Updated last year
- ☆18Sep 25, 2026Updated 2 weeks ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Alibaba Cloud AS02MC04 hack☆79Jul 17, 2026Updated 2 months ago
- Sata 2 Host Controller for FPGA implementation☆18Oct 11, 2017Updated 8 years ago
- ☆103Jun 29, 2026Updated 3 months ago
- The official repository of the local FPGA Development Kit.☆22Apr 30, 2019Updated 7 years ago
- Gowin USB3.0 Device Controller IP☆18Aug 20, 2024Updated 2 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Utilities for Avalon Memory Map☆11Jun 16, 2026Updated 3 months ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆78Jun 2, 2024Updated 2 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- 基于fpga的cordic算法实现☆13Oct 19, 2024Updated last year
- 2024年全国大学生嵌入式芯片与系统设计竞赛 FPGA创新设计赛道 国一+易灵思创新杯获奖作品 Ultra-Vision （基于Ti60F225的无极缩放算法实现）☆115Aug 29, 2026Updated last month
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP☆68Nov 12, 2022Updated 3 years ago
- All You Need to Know About QDMA☆23Jun 30, 2023Updated 3 years ago
- Cosmos OpenSSD + Hardware and Software source distribution☆261Jul 29, 2022Updated 4 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆21Jun 5, 2026Updated 4 months ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆48Sep 6, 2026Updated last month
- ☆10Nov 12, 2019Updated 6 years ago
- ☆35Jul 9, 2025Updated last year
- H265 decoder write in verilog, verified on Xilinx ZYNQ7035☆88Sep 2, 2021Updated 5 years ago
- AWGN signal generator IP for FPGA implemented by Verilog HDL with Fmax up to 320MHz on Xilinx Virtex Ultra-Scale FPGA.☆16Sep 20, 2020Updated 6 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16May 26, 2021Updated 5 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆19Aug 28, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Lattice Crosslink FPGA is programmed to simulate an IMX219 image stream to a Jetson Nano☆18Feb 10, 2021Updated 5 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆130Aug 29, 2022Updated 4 years ago
- Standalone SDR experiment using multicore MCU☆11Apr 12, 2018Updated 8 years ago
- Display something on an analog oscilloscope☆12Oct 30, 2018Updated 7 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆24Apr 27, 2023Updated 3 years ago
- Verilog PCI express components☆1,669Apr 26, 2024Updated 2 years ago
- ☆22Jul 28, 2021Updated 5 years ago