Alternatives and similar repositories for EasyAXI

Users that are interested in EasyAXI are comparing it to the libraries listed below

• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆66Updated 5 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆38Updated 3 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆73Updated 3 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆43Updated 4 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆113Updated 10 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆55Updated 8 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆147Updated 2 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆201Updated last year
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆85Updated 3 years ago
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆182Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆92Updated 5 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆63Updated 8 months ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆49Updated 6 years ago
• aq12138 / Git_Bilbili
  verilog
  ☆21Updated last year
• wudayemen / gen_apb_file
  ☆67Updated 3 years ago
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆198Updated last year
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆40Updated 3 years ago
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆46Updated 9 months ago
• ForrestBlue / cortexm0ds
  ☆62Updated 9 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆120Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆34Updated 3 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆63Updated 6 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆70Updated last year
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆35Updated last year
• john9636 / SortingNetwork
  Implement a bitonic sorting network on FPGA
  ☆42Updated 3 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆33Updated 5 years ago
• WangXuan95 / FPGA-DDR-SDRAM
  An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
  ☆176Updated last year