CMU-SAFARI / GPGPUSim-Ramulator
The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used to produce some of the results in our SIGMETRICS 2019 paper: Ghose et al., "Demystifying Complex Workload-DRAM Interactions: An Experimental Study" at https://arxiv.org/pdf/1902.07609.pdf.
☆54Updated 5 years ago
Alternatives and similar repositories for GPGPUSim-Ramulator:
Users that are interested in GPGPUSim-Ramulator are comparing it to the libraries listed below
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆21Updated 6 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated last year
- EQueue Dialect☆40Updated 3 years ago
- ☆91Updated last year
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- ☆25Updated 3 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆51Updated 4 months ago
- ☆66Updated 4 years ago
- A Cycle-level simulator for M2NDP☆26Updated 4 months ago
- Heterogeneous simulator for DECADES Project☆32Updated 11 months ago
- agile hardware-software co-design☆46Updated 3 years ago
- ☆72Updated 4 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆64Updated 9 months ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆49Updated 8 months ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆36Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- Artifact, reproducibility, and testing utilites for gem5☆21Updated 3 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆26Updated last year
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆49Updated last month
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 2 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- PIM-ML is a benchmark for training machine learning algorithms on the UPMEM architecture, which is the first publicly-available real-worl…☆23Updated 3 months ago
- Source code of the simulator used in the Mosaic paper from MICRO 2017: "Mosaic: A GPU Memory Manager with Application-Transparent Support…☆46Updated 6 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is inte…☆81Updated last year
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- Release of stream-specialization software/hardware stack.☆121Updated last year