g0kul / vcnnLinks
Verilog Convolutional Neural Network on PYNQ
☆28Updated 7 years ago
Alternatives and similar repositories for vcnn
Users that are interested in vcnn are comparing it to the libraries listed below
Sorting:
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆99Updated last year
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- A convolutional neural network implemented in hardware (verilog)☆161Updated 8 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆84Updated 6 years ago
- ☆90Updated 5 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆74Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆185Updated 8 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- ☆48Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 7 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆188Updated last year
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- 中文:☆103Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆160Updated 6 years ago
- ☆68Updated 6 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago