gr-rahimi / APSimLinks
☆22Updated 4 years ago
Alternatives and similar repositories for APSim
Users that are interested in APSim are comparing it to the libraries listed below
Sorting:
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 8 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆57Updated 6 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆49Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆52Updated 8 years ago
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆19Updated 6 years ago
- ☆14Updated 2 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 7 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 3 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- EQueue Dialect☆39Updated 3 years ago
- ☆58Updated 2 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- ☆30Updated 6 years ago
- ☆29Updated 8 years ago
- STONNE Simulator integrated into SST Simulator☆21Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆130Updated 5 years ago
- ☆24Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 4 years ago
- ☆19Updated 4 years ago