gr-rahimi / APSim
☆23Updated 3 years ago
Alternatives and similar repositories for APSim:
Users that are interested in APSim are comparing it to the libraries listed below
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆23Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆18Updated 4 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 5 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆17Updated 6 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 5 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated 11 months ago
- DASS HLS Compiler☆27Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- ☆27Updated 3 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆19Updated 4 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆27Updated 4 years ago
- ☆18Updated 3 years ago
- ☆26Updated 7 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆20Updated last week
- Project repo for the POSH on-chip network generator☆43Updated last year
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆17Updated 4 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated last month
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆60Updated last year
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago