gr-rahimi / APSimLinks
☆22Updated 4 years ago
Alternatives and similar repositories for APSim
Users that are interested in APSim are comparing it to the libraries listed below
Sorting:
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆44Updated 7 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆24Updated 5 years ago
- EQueue Dialect☆42Updated 4 years ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆53Updated this week
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆23Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 4 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆59Updated 6 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆21Updated 7 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- A graph linear algebra overlay☆51Updated 2 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Domain-Specific Architecture Generator 2☆22Updated 3 years ago
- ☆14Updated 3 years ago
- The OpenPiton Platform☆28Updated 2 years ago
- Heterogeneous simulator for DECADES Project☆32Updated last year
- ☆30Updated 6 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆20Updated last week
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Updated 7 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆26Updated 3 years ago