gr-rahimi / APSimLinks
☆22Updated 4 years ago
Alternatives and similar repositories for APSim
Users that are interested in APSim are comparing it to the libraries listed below
Sorting:
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 4 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆24Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- ☆60Updated 2 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- ☆14Updated 2 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- FPGA version of Rodinia in HLS C/C++☆40Updated 5 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆29Updated 8 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- ☆13Updated 3 years ago
- HLS project modeling various sparse accelerators.☆12Updated 4 years ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆53Updated last week
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆20Updated 7 years ago
- ☆36Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated last week
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- The OpenPiton Platform☆28Updated 2 years ago
- ☆30Updated 6 years ago