Alternatives and similar repositories for TinkerCAD_Arduino

Users that are interested in TinkerCAD_Arduino are comparing it to the libraries listed below

• circuit-solver / circuit-solver.github.io
  This is Circuit Solver which can solve any kind of circuit for you. Do check it out!!
  ☆11Updated 3 years ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆36Updated 2 years ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆124Updated 3 years ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• arunkpv / vsd-hdp
  ☆18Updated 2 months ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆407Updated last year
• amd / Kria-RoboticsAI
  ☆17Updated 2 years ago
• mehwish411 / 5-Staged-Pipelined-RISC-V-32I-Processor
  5 stage pipeline implementation of RISC-V 32I Processor.
  ☆10Updated last year
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆16Updated 2 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆82Updated 2 years ago
• Subhasis-Sahu / SFAL-VSD
  ☆13Updated last year
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆31Updated last year
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆20Updated last year
• Rishabh-zhcet / 3DOF_RoboticArmFPGA
  This repository contains the details of controlling a 3-DOF robotic arm with 4 servo motors using FPGA. The design is execute using the N…
  ☆21Updated 3 years ago
• TheLeopardsH / RISC-V-5-stage-pipelined-in-verilog
  RISC-V-5 stage pipelined in verilog
  ☆10Updated 5 years ago
• aseddin / ece_4305
  Code associated with Cal Poly Pomona's ECE 4305
  ☆38Updated 4 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆82Updated last month
• aklsh / getting-started-with-verilog
  Verilog modules for beginners
  ☆28Updated 3 years ago
• tomas-fryza / vhdl-examples
  VHDL course at Brno University of Technology
  ☆128Updated this week
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆291Updated 8 months ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆107Updated 3 years ago
• os-fpga / Virtual-FPGA-Lab
  This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…
  ☆237Updated 7 months ago
• rigoorozco / m2-artix7-accelerator-card
  M.2 PCIe Artix 7 FPGA Accelerator Card
  ☆17Updated 10 months ago
• supratimdas / NoobsCpu-8bit
  A simple 8bit CPU.
  ☆26Updated last year
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆164Updated last year
• visnjicm / verilog-neural-network
  Verilog implementation of a pre-trained handwritten digit recognition simple neural network.
  ☆27Updated 2 years ago
• matbi86 / 01_ai_accelerator_basic_for_student
  ai_accelerator_basic_for_student (no solve)
  ☆13Updated 5 years ago
• harshithsn / Universal-Shift-Register
  This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…
  ☆11Updated 3 years ago
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆202Updated last month
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆59Updated last year