Alternatives and similar repositories for core_jpeg:

Users that are interested in core_jpeg are comparing it to the libraries listed below

• freecores / jpegencode
  JPEG Encoder Verilog
  ☆74Updated 2 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆276Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆421Updated 3 years ago
• ultraembedded / FPGAmp
  720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
  ☆275Updated 4 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆121Updated 2 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆312Updated 10 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆88Updated 5 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆242Updated last year
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆144Updated 2 weeks ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆129Updated 2 years ago
• WangXuan95 / FPGA-MPEG2-encoder
  An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。
  ☆120Updated last year
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆112Updated last year
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆250Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆523Updated last month
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆228Updated 2 years ago
• projf / display_controller
  FPGA display controller with support for VGA, DVI, and HDMI.
  ☆224Updated 5 years ago
• benreynwar / fft-dit-fpga
  Verilog module for calculation of FFT.
  ☆167Updated 12 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆79Updated 4 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆290Updated last year
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆124Updated 10 years ago
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆242Updated 5 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆121Updated 3 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆134Updated 2 weeks ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆93Updated 4 years ago
• openasic-org / xk265
  xk265：HEVC/H.265 Video Encoder IP Core (RTL)
  ☆241Updated last year
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆115Updated 5 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆122Updated 4 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆193Updated 7 months ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆153Updated last year