ultraembedded / core_jpegLinks
High throughput JPEG decoder in Verilog for FPGA
☆253Updated 3 years ago
Alternatives and similar repositories for core_jpeg
Users that are interested in core_jpeg are comparing it to the libraries listed below
Sorting:
- Opensource DDR3 Controller☆410Updated 2 weeks ago
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆292Updated 5 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆555Updated 4 years ago
- JPEG Encoder Verilog☆79Updated 3 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆414Updated 4 months ago
- Verilog UART☆191Updated 12 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆150Updated 2 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆265Updated 6 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆284Updated 5 years ago
- WISHBONE SD Card Controller IP Core☆130Updated 3 years ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- A simple implementation of a UART modem in Verilog.☆172Updated 4 years ago
- FPGA display controller with support for VGA, DVI, and HDMI.☆246Updated this week
- A full-speed device-side USB peripheral core written in Verilog.☆236Updated 3 years ago
- Verilog digital signal processing components☆169Updated 3 years ago
- IEEE 754 floating point unit in Verilog☆149Updated 9 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆351Updated 3 months ago
- A simple, basic, formally verified UART controller☆321Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Updated 11 months ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆142Updated 2 years ago
- Fixed Point Math Library for Verilog☆145Updated 11 years ago
- Pipeline FFT Implementation in Verilog HDL☆157Updated 6 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆223Updated 5 years ago
- Verilog module for calculation of FFT.☆191Updated 13 years ago
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- AHB3-Lite Interconnect☆109Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- Verilog Configurable Cache☆192Updated this week
- Simple 8-bit UART realization on Verilog HDL.☆114Updated last year