ultraembedded / core_jpegLinks
High throughput JPEG decoder in Verilog for FPGA
☆233Updated 3 years ago
Alternatives and similar repositories for core_jpeg
Users that are interested in core_jpeg are comparing it to the libraries listed below
Sorting:
- Opensource DDR3 Controller☆347Updated last week
- A DDR3 memory controller in Verilog for various FPGAs☆475Updated 3 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆353Updated last year
- WISHBONE SD Card Controller IP Core☆124Updated 2 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆294Updated 2 months ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆264Updated this week
- Verilog digital signal processing components☆143Updated 2 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆232Updated 2 years ago
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆279Updated 4 years ago
- JPEG Encoder Verilog☆76Updated 2 years ago
- Verilog module for calculation of FFT.☆175Updated 12 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆250Updated 6 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆149Updated 3 months ago
- FPGA display controller with support for VGA, DVI, and HDMI.☆230Updated 5 years ago
- Fixed Point Math Library for Verilog☆132Updated 10 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆207Updated last year
- AXI interface modules for Cocotb☆267Updated last year
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆125Updated last year
- Bus bridges and other odds and ends☆568Updated 2 months ago
- Basic RISC-V Test SoC☆129Updated 6 years ago
- SPI Slave for FPGA in Verilog and VHDL☆201Updated last year
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆123Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆214Updated 4 years ago
- A simple, basic, formally verified UART controller☆304Updated last year
- IEEE 754 floating point unit in Verilog☆138Updated 9 years ago
- Verilog UART☆172Updated 12 years ago
- Common SystemVerilog components☆629Updated this week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆269Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆85Updated 6 years ago