Alternatives and similar repositories for opencores-ip

Users that are interested in opencores-ip are comparing it to the libraries listed below

• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆159Updated 6 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆392Updated 5 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆115Updated last year
• jamieiles / uart
  Verilog UART
  ☆186Updated 12 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆186Updated last month
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆215Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆528Updated 4 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆181Updated last year
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆309Updated 2 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆183Updated this week
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆144Updated 11 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆79Updated 2 weeks ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆155Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 8 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆390Updated 2 months ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆144Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 5 months ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• mattvenn / awesome-opensource-asic-resources
  ☆359Updated 2 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆128Updated 3 years ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆235Updated 3 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆297Updated last month
• raysalemi / Python4RTLVerification
  ☆168Updated 3 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆164Updated 4 years ago
• HDLForBeginners / Examples
  ☆110Updated 2 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆123Updated 5 years ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆97Updated 4 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆316Updated last year