A huge collection of VHDL/Verilog open-source IP cores scraped from the web
☆151Oct 27, 2015Updated 10 years ago
Alternatives and similar repositories for opencores-ip
Users that are interested in opencores-ip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- few python scripts to clone all IP cores from opencores.org☆29Jan 8, 2024Updated 2 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆623Jan 18, 2023Updated 3 years ago
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆11Jun 2, 2021Updated 5 years ago
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆69Jan 10, 2024Updated 2 years ago
- 10G Low Latency Ethernet☆110Jul 15, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆21Apr 12, 2026Updated 4 months ago
- ☆24Jun 17, 2014Updated 12 years ago
- RISC-V Ibex core with Wishbone B4 interface☆22May 30, 2026Updated 2 months ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆13Sep 3, 2019Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆36Jun 27, 2024Updated 2 years ago
- FPGA, CuDNN/CUDA & C++ Hybrid infrastructure for ultra low-latency algorithmic trading. Implements market data parsing, order book manage…☆22Apr 24, 2026Updated 3 months ago
- 24bit CPU with integrated GPU made in Logisim☆15Mar 3, 2026Updated 5 months ago
- ☆208Oct 17, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆99Updated this week
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆59Mar 3, 2024Updated 2 years ago
- ☆12Apr 3, 2017Updated 9 years ago
- ☆23Apr 24, 2026Updated 3 months ago
- A roadmap for those who want to build a career as an FPGA / ASIC Engineer☆676May 31, 2026Updated 2 months ago
- This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined conf…☆20Apr 26, 2023Updated 3 years ago
- Supercharged USB bootloader for various PIC24/dsPIC33 MCUs.☆12Jul 8, 2021Updated 5 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆19Jan 28, 2022Updated 4 years ago
- C++ implementation of Reed-Solomon encoding/decoding☆18Feb 9, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RMII Firewall FPGA☆25Dec 2, 2019Updated 6 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- PW-Sat2 hardware designed by the PW-Sat2 team☆12May 20, 2019Updated 7 years ago
- To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA pla…☆42Dec 24, 2020Updated 5 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆25Nov 9, 2025Updated 9 months ago
- TCL scripts for FPGA (Xilinx)☆36Jul 5, 2022Updated 4 years ago
- ☆18Jun 2, 2025Updated last year
- VHDL Implementation☆15Oct 9, 2014Updated 11 years ago
- Hack@DAC 2021☆20Jul 24, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆120May 11, 2023Updated 3 years ago
- softcore for ForwardCom☆22Jan 1, 2023Updated 3 years ago
- Open Logic FPGA Standard Library☆998Updated this week
- OneWire library custom engineered for JLD505 boards with DS2480B chips☆11Jul 1, 2015Updated 11 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Aug 6, 2026Updated last week
- Homework assignments for CIS 4710/5710☆35Apr 29, 2026Updated 3 months ago
- RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.☆113Dec 24, 2023Updated 2 years ago