Alternatives and similar repositories for opencores-ip

Users that are interested in opencores-ip are comparing it to the libraries listed below

• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆383Updated 3 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆155Updated 2 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆144Updated 6 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆108Updated last year
• jamieiles / uart
  Verilog UART
  ☆180Updated 12 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆378Updated last week
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆146Updated 4 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆76Updated 3 months ago
• HDLForBeginners / Examples
  ☆103Updated 2 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆180Updated last week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆512Updated 3 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆172Updated 4 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆127Updated 3 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆379Updated this week
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆143Updated 11 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆348Updated 6 months ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆211Updated last year
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆310Updated last year
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆109Updated last year
• raysalemi / Python4RTLVerification
  ☆165Updated 3 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆175Updated 10 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆283Updated 2 weeks ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆69Updated 9 months ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆156Updated 6 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆346Updated 2 years ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆520Updated 2 years ago
• FPGADude / Digital-Design
  Verilog HDL files
  ☆153Updated last year
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆155Updated 3 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆342Updated 8 years ago