Alternatives and similar repositories for awesome-vhdl:

Users that are interested in awesome-vhdl are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆124Updated 3 weeks ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆64Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆47Updated this week
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆143Updated this week
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆52Updated this week
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆94Updated 2 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆169Updated this week
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆74Updated last year
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆113Updated last year
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 8 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆79Updated 4 years ago
• pieter3d / simview
  ☆76Updated 10 months ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆170Updated 3 weeks ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆55Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆78Updated last month
• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆42Updated 4 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆124Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 7 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 3 years ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆77Updated 2 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆186Updated last year
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆72Updated 2 years ago
• suoto / fpga_cores
  ☆32Updated last year
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 3 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆32Updated 4 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆32Updated last month
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆82Updated 6 months ago