Alternatives and similar repositories for awesome-vhdl

Users that are interested in awesome-vhdl are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆148Updated 5 months ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• pieter3d / simview
  ☆87Updated last month
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 10 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• ldoolitt / vhd2vl
  ☆137Updated 11 months ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆164Updated this week
• kevinpt / symbolator
  HDL symbol generator
  ☆197Updated 2 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆132Updated last year
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated last year
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆84Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 9 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆58Updated this week
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆38Updated 4 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 3 years ago
• ghdl / docker
  Scripts to build and use docker images including GHDL
  ☆43Updated last year
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆48Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 9 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆71Updated this week
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆73Updated 3 years ago
• davidthings / tinyfpga_bx_usbserial
  USB Serial on the TinyFPGA BX
  ☆135Updated 4 years ago