Alternatives and similar repositories for awesome-vhdl

Users that are interested in awesome-vhdl are comparing it to the libraries listed below

• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆185Updated this week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 11 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• ldoolitt / vhd2vl
  ☆138Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆49Updated 3 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated 2 years ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆167Updated last week
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆89Updated last year
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated last week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last month
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆200Updated 2 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆85Updated 2 years ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆81Updated last month
• pieter3d / simview
  ☆88Updated 3 months ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated 2 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆60Updated last week
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆39Updated 10 months ago