Floating-point matrix multiplication implementation (arbitrary precision)
☆17Aug 3, 2021Updated 4 years ago
Alternatives and similar repositories for float-matmul
Users that are interested in float-matmul are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FPGA and CPU-Based power system's simulator☆21Apr 7, 2021Updated 4 years ago
- ☆15Oct 31, 2021Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆46Jun 24, 2022Updated 3 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 3 years ago
- Implementation for paper "BATMANN: A Binarized-All-Through Memory-Augmented Neural Network for Efficient In-Memory Computing"☆12Jan 12, 2022Updated 4 years ago
- 3D-FPIM: An Extreme Energy-Efficient DNN Acceleration System Using 3D NAND Flash-Based In-Situ PIM Unit (MICRO 2022)☆20May 19, 2023Updated 2 years ago
- ☆19Dec 3, 2019Updated 6 years ago
- VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and …☆24Oct 29, 2025Updated 4 months ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Sep 3, 2019Updated 6 years ago
- Matrix multiplication on multiple Nios II cores☆16Feb 12, 2020Updated 6 years ago
- FPGA-based SNN Accelerator Toy☆36Dec 17, 2025Updated 3 months ago
- ☆14Mar 9, 2026Updated 2 weeks ago
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 7 months ago
- practice configure AHB-Lite bus protocol☆19Mar 11, 2019Updated 7 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆28Apr 7, 2025Updated 11 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆15Jun 23, 2020Updated 5 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- SGMII☆13Jul 17, 2014Updated 11 years ago
- Deprecated, please use https://github.com/Nuclei-Software/nuclei-sdk☆21Mar 24, 2021Updated 5 years ago
- ☆21Apr 28, 2021Updated 4 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Mar 24, 2021Updated 5 years ago
- ☆10Jul 14, 2018Updated 7 years ago
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- Read arm docs, and translate these docs to chinese.☆20Jun 5, 2018Updated 7 years ago
- Simple sram controller in verilog.☆36Jun 5, 2016Updated 9 years ago
- VR Joystick Teleoperation for Isaac Lab with Meta Quest☆19May 10, 2025Updated 10 months ago
- VPN system for accessing network in firewall (using Wireguard)☆14Mar 26, 2021Updated 4 years ago
- An application for turning PornHub images into ASCII art. Created for SexTechHack 2016.☆29Jun 10, 2021Updated 4 years ago
- Ethernet-MAC System verilog☆12May 28, 2018Updated 7 years ago
- Massively Parallel ANS Decoding on GPUs☆30Jul 26, 2019Updated 6 years ago
- IC implementation of Systolic Array for TPU☆343Oct 21, 2024Updated last year
- Tutorials on Vitis AI Created by LogicTronix!☆35Jul 5, 2024Updated last year
- ☆18Aug 20, 2025Updated 7 months ago
- PCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambl…☆15Jul 5, 2025Updated 8 months ago
- Library of FPGA architectures☆31Mar 9, 2026Updated 2 weeks ago