Alternatives and similar repositories for oram:

Users that are interested in oram are comparing it to the libraries listed below

• kwonalbert / oram_fpga
  FPGA related files for ORAM
  ☆12Updated 9 years ago
• dskarlatos / ElasticCuckooHashing
  (elastic) cuckoo hashing
  ☆14Updated 4 years ago
• umd-memsys / gem5
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆11Updated 4 years ago
• WukLab / FPGA-OS
  ☆33Updated 4 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆22Updated 6 months ago
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 5 years ago
• pranith / usimm
  USIMM: the Utah SImulated Memory Module
  ☆22Updated 10 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• efeslab / lapidary
  Creating beautiful gem5 simulations
  ☆47Updated 4 years ago
• parsa-epfl / qflex
  Quick & Flexible Rack-Scale Computer Architecture Simulator
  ☆36Updated 3 weeks ago
• Krishnaps / Gem5-PCI-Express
  Gem5 with PCI Express integrated.
  ☆17Updated 6 years ago
• darchr / gem5art
  Artifact, reproducibility, and testing utilites for gem5
  ☆21Updated 3 years ago
• SwarmArch / sim
  ordspecsim: The Swarm architecture simulator
  ☆24Updated 2 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• ascend-secure-processor / oram
  Hardware implementation of ORAM
  ☆22Updated 7 years ago
• cwfletcher / stt
  ☆35Updated 4 years ago
• jimstevens2001 / HybridSim
  Simulator of a memory controller to connect DRAMSim and FlashDIMMSim into one unified memory
  ☆17Updated 11 months ago
• PrincetonUniversity / MosaicSim
  Heterogeneous simulator for DECADES Project
  ☆32Updated 10 months ago
• m-asiatici / MSHR-rich
  A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…
  ☆18Updated 4 years ago
• aakahlow / gem5Valid_Haswell
  ☆18Updated 5 years ago
• stanford-mast / ShEF
  Shielded Enclaves for Cloud FPGAs
  ☆15Updated 3 years ago
• CMU-SAFARI / MemBen
  Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …
  ☆20Updated 4 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆12Updated last year
• PrincetonUniversity / primesim
  A parallel and distributed simulator for thousand-core chips
  ☆24Updated 6 years ago
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆41Updated 7 years ago
• UCLA-SEAL / HeteroGen
  HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
  ☆17Updated 6 months ago
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆32Updated 4 years ago
• maltanar / fpga-booleanring-bfs
  Hybrid BFS on Xilinx Zynq
  ☆18Updated 9 years ago
• efeslab / optimus-hypervisor
  ☆19Updated 4 years ago
• jkadlec / gem5-l3-mesif
  MESIF cache coherency protocol for the GEM5 simulator
  ☆14Updated 8 years ago