OpenVADL / openvadlLinks
An open-source implementation of the VADL processor description language.
☆36Updated this week
Alternatives and similar repositories for openvadl
Users that are interested in openvadl are comparing it to the libraries listed below
Sorting:
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆149Updated last week
- Xtext project to parse CoreDSL files☆24Updated last month
- ☆57Updated 3 years ago
- Verik toolchain☆45Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- ☆87Updated 3 weeks ago
- Logic circuit analysis and optimization☆42Updated 3 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- Debuggable hardware generator☆70Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆88Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- FPGA Assembly (FASM) Parser and Generator☆97Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- ☆104Updated 3 years ago
- A SystemVerilog language server based on the Slang library.☆64Updated this week
- Chisel/Firrtl execution engine☆153Updated last year
- firrtlator is a FIRRTL C++ library☆23Updated 8 years ago
- 21st century electronic design automation tools, written in Rust.☆32Updated this week
- Proposed RISC-V Composable Custom Extensions Specification