tum-ei-eda / seal5
Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization
☆17Updated this week
Alternatives and similar repositories for seal5:
Users that are interested in seal5 are comparing it to the libraries listed below
- Xtext project to parse CoreDSL files☆18Updated 2 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆106Updated last year
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- Chisel RISC-V Vector 1.0 Implementation☆93Updated last week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated last week
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆24Updated last month
- The specification for the FIRRTL language☆54Updated this week
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆19Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆28Updated 2 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- Intel Compiler for SystemC☆23Updated last year
- HeteroCL-MLIR dialect for accelerator design☆40Updated 7 months ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆99Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated this week
- Pulp virtual platform☆23Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- A libgloss replacement for RISC-V that supports HTIF☆34Updated 11 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆25Updated 2 weeks ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆14Updated 5 months ago
- ☆40Updated 3 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- ☆15Updated 4 years ago
- ☆33Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- Example for running IREE in a bare-metal Arm environment.☆33Updated last month
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated last week