tum-ei-eda / seal5Links
Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization
☆23Updated last week
Alternatives and similar repositories for seal5
Users that are interested in seal5 are comparing it to the libraries listed below
Sorting:
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- A hardware synthesis framework with multi-level paradigm☆41Updated 9 months ago
- Chisel RISC-V Vector 1.0 Implementation☆118Updated last month
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆23Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆43Updated 4 months ago
- ☆37Updated last year
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆141Updated this week
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- ☆17Updated 7 months ago
- ☆47Updated 9 months ago
- RiVEC Bencmark Suite☆122Updated 11 months ago
- ☆18Updated 4 months ago
- Vector Acceleration IP core for RISC-V*☆184Updated 5 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆34Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆106Updated last month
- high-performance RTL simulator☆181Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- The OpenPiton Platform☆28Updated 2 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆108Updated 5 months ago
- ☆60Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆75Updated 3 weeks ago
- A libgloss replacement for RISC-V that supports HTIF☆38Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆123Updated this week
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆109Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 4 months ago
- ☆33Updated this week