Alternatives and similar repositories for MIT_Bluespec_RISCV_Tutorial:

Users that are interested in MIT_Bluespec_RISCV_Tutorial are comparing it to the libraries listed below

• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆36Updated last year
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆14Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• datenlord / training
  ☆9Updated last year
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆23Updated 2 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆38Updated last year
• Jpz-sdju / trinity
  ☆19Updated 2 weeks ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆50Updated 3 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆33Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 10 months ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆19Updated 6 years ago
• USTC-System-Courses / CECS-Lab
  ☆34Updated last year
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆14Updated last week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆76Updated last year
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated 9 months ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆34Updated last year
• RealJustinNi / EE219-AICS-2024
  ☆11Updated 2 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆48Updated 4 months ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆22Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆41Updated 2 weeks ago
• OSCPU / ysyxSoC
  ☆80Updated last month
• ysyx-ta / ysyx-summer-readings
  ☆63Updated 7 months ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆30Updated 2 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆30Updated 11 months ago
• CherrySprings / CherrySprings
  ☆17Updated last year
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆26Updated 5 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆10Updated last month