fpgasystems / ZipML-XeonFPGALinks
FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)
☆33Updated 5 years ago
Alternatives and similar repositories for ZipML-XeonFPGA
Users that are interested in ZipML-XeonFPGA are comparing it to the libraries listed below
Sorting:
- CNN accelerator☆27Updated 8 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆55Updated 7 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- DASS HLS Compiler☆29Updated last year
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- ☆88Updated 2 years ago
- ☆15Updated 4 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- ☆66Updated 2 years ago
- Public release☆57Updated 5 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Updated 5 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆48Updated 9 years ago
- MAERI public release☆31Updated 3 years ago
- ☆58Updated 5 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago