fpgasystems / ZipML-XeonFPGALinks
FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)
☆33Updated 6 years ago
Alternatives and similar repositories for ZipML-XeonFPGA
Users that are interested in ZipML-XeonFPGA are comparing it to the libraries listed below
Sorting:
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆55Updated 8 years ago
- CNN accelerator☆29Updated 8 years ago
- ☆15Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Updated 5 years ago
- ☆88Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13Updated 9 years ago
- MAESTRO binary release☆22Updated 6 years ago
- MAERI public release☆31Updated 4 years ago
- Public release☆58Updated 6 years ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 8 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- ☆29Updated 8 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆28Updated 8 years ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Updated 3 years ago