fpgasystems / ZipML-XeonFPGA
FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)
☆33Updated 5 years ago
Alternatives and similar repositories for ZipML-XeonFPGA:
Users that are interested in ZipML-XeonFPGA are comparing it to the libraries listed below
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆53Updated 7 years ago
- CNN accelerator☆27Updated 7 years ago
- ☆15Updated 4 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆59Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Introductory examples for using PYNQ with Alveo☆51Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- MAERI public release☆31Updated 3 years ago
- ☆23Updated 4 years ago
- ☆71Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆62Updated 3 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated last week
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 7 years ago
- ☆40Updated 5 years ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated 10 months ago
- MAESTRO binary release☆22Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- DASS HLS Compiler☆28Updated last year
- Project repo for the POSH on-chip network generator☆43Updated last year
- first-order deep learning accelerator model☆18Updated 7 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 8 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Public release☆49Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year