fpgasystems / ZipML-XeonFPGALinks
FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)
☆33Updated 5 years ago
Alternatives and similar repositories for ZipML-XeonFPGA
Users that are interested in ZipML-XeonFPGA are comparing it to the libraries listed below
Sorting:
- CNN accelerator☆28Updated 8 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆55Updated 8 years ago
- ☆15Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- Public release☆58Updated 6 years ago
- ☆88Updated 3 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Updated 2 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆26Updated 3 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- ☆29Updated 8 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- A floating-point matrix multiplication implemented in hardware☆32Updated 5 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13Updated 9 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 8 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆72Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆32Updated 2 years ago