Alternatives and similar repositories for leon3-grlib-gpl-mirror

Users that are interested in leon3-grlib-gpl-mirror are comparing it to the libraries listed below

• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated last month
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆29Updated 5 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆31Updated 4 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆66Updated last week
• lnls-dig / general-cores
  general-cores
  ☆20Updated 2 weeks ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆22Updated 3 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• mcci-catena / catena-riscv32-fpga
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Updated 6 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆13Updated 3 weeks ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated this week
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• enjoy-digital / litesata_axiom
  ☆12Updated 4 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆27Updated 5 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆24Updated 3 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆17Updated 4 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated this week
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆46Updated 5 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• buttercutter / noc
  A simple spidergon network-on-chip with wormhole switching feature
  ☆12Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆22Updated last week
• b224hisl / rioschip
  ☆33Updated 2 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆31Updated 7 months ago