MATCHA-MIT / PensieveLinks
This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
☆23Updated last year
Alternatives and similar repositories for Pensieve
Users that are interested in Pensieve are comparing it to the libraries listed below
Sorting:
- ☆35Updated 4 years ago
- CleanupSpec (MICRO-2019)☆17Updated 4 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆27Updated 2 years ago
- ☆18Updated 2 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Updated 5 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆20Updated 4 years ago
- ☆25Updated 2 years ago
- Proof of concept code for the BranchSpec exploit.☆9Updated 2 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆15Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆25Updated 8 months ago
- HW interface for memory caches☆28Updated 5 years ago
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆48Updated 5 years ago
- MIRAGE (USENIX Security 2021)☆13Updated last year
- ☆12Updated 4 years ago
- Microscope: Enabling Microarchitectural Replay Attacks☆19Updated 4 years ago
- New Cache implementation using Gem5☆13Updated 11 years ago
- The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆21Updated last year
- Security Test Benchmark for Computer Architectures☆21Updated 3 months ago
- ☆15Updated 2 months ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆19Updated 3 months ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆67Updated 2 months ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems [USENIX Security '23]☆18Updated 2 years ago
- ☆19Updated 2 years ago
- ☆32Updated 5 years ago
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆17Updated last year
- ☆12Updated 5 years ago