facebookresearch / AutoCATLinks
AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks
☆45Updated 2 years ago
Alternatives and similar repositories for AutoCAT
Users that are interested in AutoCAT are comparing it to the libraries listed below
Sorting:
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆21Updated 2 years ago
- ☆9Updated 2 years ago
- ☆13Updated 4 years ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆17Updated 2 years ago
- CleanupSpec (MICRO-2019)☆17Updated 4 years ago
- ☆31Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆25Updated 3 weeks ago
- ☆35Updated 6 years ago
- ☆85Updated 2 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆20Updated 4 years ago
- MIRAGE (USENIX Security 2021)☆13Updated last year
- Fix syntax errors of LLM-generated RTL☆36Updated last year
- ☆9Updated 9 years ago
- ☆25Updated 2 years ago
- ☆11Updated 2 weeks ago
- ☆19Updated 3 years ago
- Microscope: Enabling Microarchitectural Replay Attacks☆19Updated 5 years ago
- BiSUNA framework specialized to compile for the Xilinx Alveo U50☆12Updated 4 years ago
- Memory consistency model checking and test generation library.☆15Updated 8 years ago
- BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…☆19Updated 4 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Updated 5 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆27Updated 2 years ago
- ☆25Updated 5 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆69Updated 4 months ago
- ☆18Updated 3 years ago
- ☆35Updated 4 years ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆87Updated 2 weeks ago
- The MiBench testsuite, extended for use in general embedded environments☆101Updated 12 years ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 9 years ago