facebookresearch / AutoCAT
AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks
☆44Updated last year
Alternatives and similar repositories for AutoCAT:
Users that are interested in AutoCAT are comparing it to the libraries listed below
- ☆9Updated 2 years ago
- ☆12Updated 4 years ago
- CleanupSpec (MICRO-2019)☆17Updated 4 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 4 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆20Updated 4 years ago
- MIRAGE (USENIX Security 2021)☆12Updated last year
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆21Updated 2 years ago
- ☆80Updated 2 years ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆17Updated last year
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆24Updated 7 months ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆15Updated 3 years ago
- ☆19Updated 2 years ago
- ☆24Updated 2 years ago
- ☆31Updated 2 years ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆72Updated 7 months ago
- BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…☆19Updated 4 years ago
- ☆17Updated 3 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Updated 5 years ago
- ☆11Updated 2 months ago
- ☆17Updated 2 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆27Updated 2 years ago
- Memory consistency model checking and test generation library.☆15Updated 8 years ago
- ☆11Updated last year
- Reload+Refresh PoC☆14Updated 5 years ago
- Security Test Benchmark for Computer Architectures☆21Updated 2 months ago
- Proof of concept code for the BranchSpec exploit.☆9Updated 2 years ago
- New Cache implementation using Gem5☆13Updated 11 years ago
- ☆11Updated 2 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆65Updated last month
- ☆14Updated last month