Alternatives and similar repositories for dolma

Users that are interested in dolma are comparing it to the libraries listed below

• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆16Updated 5 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆61Updated 5 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 4 months ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆28Updated 7 months ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆22Updated 4 years ago
• cwfletcher / stt
  ☆34Updated last month
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 6 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆31Updated 3 years ago
• ctrippel / checkmate
  ☆36Updated 6 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆14Updated 2 years ago
• vusec / tlbdr
  ☆17Updated 3 years ago
• PittECEArch / AdversarialPrefetch
  ☆21Updated 3 years ago
• dskarlatos / MicroScope
  Microscope: Enabling Microarchitectural Replay Attacks
  ☆20Updated 5 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆23Updated 3 years ago
• greenlsi / reload_refresh
  Reload+Refresh PoC
  ☆16Updated 5 years ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• eepalms / gem5-newcache
  New Cache implementation using Gem5
  ☆13Updated 11 years ago
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆24Updated 2 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆28Updated 5 years ago
• compsec-snu / difuzz-rtl
  ☆101Updated last year
• ECLab-ITU / Cache-Side-Channel-Attacks
  This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.
  ☆57Updated 6 years ago
• googleinterns / hw-fuzzing
  ☆88Updated 3 years ago
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 4 years ago
• Compass-All / CCS22-StrongBox
  ☆34Updated 3 years ago
• facebookresearch / AutoCAT
  AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks
  ☆46Updated 2 years ago
• riscv / riscv-memory-tagging
  Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
  ☆26Updated last month
• TheNetAdmin / NVLeak
  NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems [USENIX Security '23]
  ☆19Updated 3 years ago
• flowyroll / uarchsec
  ☆48Updated 7 years ago
• yshalabi / covert-channel-tutorial
  Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…
  ☆53Updated 6 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 7 years ago