The artifact for SecSMT paper -- Usenix Security 2022
☆31Oct 4, 2022Updated 3 years ago
Alternatives and similar repositories for SecSMT_Artifact
Users that are interested in SecSMT_Artifact are comparing it to the libraries listed below
Sorting:
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Nov 6, 2019Updated 6 years ago
- ☆14Feb 18, 2021Updated 5 years ago
- CleanupSpec (MICRO-2019)☆16Oct 22, 2020Updated 5 years ago
- NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems [USENIX Security '23]☆19Nov 17, 2022Updated 3 years ago
- Website and PoC collection for transient execution attacks☆203Mar 9, 2024Updated last year
- Implementation for the DIMVA'22 paper "Branch Different - Spectre Attacks on Apple Silicon"☆39Jul 29, 2022Updated 3 years ago
- ☆25Mar 1, 2023Updated 3 years ago
- HW interface for memory caches☆28Apr 21, 2020Updated 5 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆61Apr 27, 2020Updated 5 years ago
- Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)☆33Aug 30, 2023Updated 2 years ago
- Proof-of-concept code for the SMoTherSpectre exploit.☆77Nov 12, 2019Updated 6 years ago
- Microarchitectural exploitation and other hardware attacks.☆96Mar 25, 2024Updated last year
- The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆22Nov 23, 2023Updated 2 years ago
- InSpectre Gadget: in-depth inspection and exploitability analysis of Spectre disclosure gadgets☆60Feb 20, 2026Updated last week
- ☆19Feb 18, 2021Updated 5 years ago
- Medusa Repository: Transynther tool and Medusa Attack☆23Jul 17, 2020Updated 5 years ago
- ☆34Dec 14, 2025Updated 2 months ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆62Aug 7, 2022Updated 3 years ago
- This upload contains the artifacts for the paper "SLAP: Data Speculation Attacks via Load Address Prediction on Apple Silicon", to appear…☆22Jan 26, 2025Updated last year
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆24Jan 17, 2024Updated 2 years ago
- ☆119Nov 14, 2022Updated 3 years ago
- ☆45Jul 19, 2023Updated 2 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆22Feb 18, 2021Updated 5 years ago
- Proof-of-concept implementation for the paper "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channel…☆27Nov 30, 2023Updated 2 years ago
- This repository contains the sources and documentation for the LVI-LFB Control Flow Hijacking attack PoC (CVE-2020-0551)☆26Mar 10, 2020Updated 5 years ago
- ☆11Nov 27, 2024Updated last year
- Revizor - Hardware fuzzing for the age of speculation☆179Feb 23, 2026Updated last week
- Tool for testing and finding minimal eviction sets☆108May 6, 2021Updated 4 years ago
- Software artifacts for "UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and Performance" (…☆11Dec 27, 2021Updated 4 years ago
- (elastic) cuckoo hashing☆16Jun 20, 2020Updated 5 years ago
- ☆48Dec 19, 2018Updated 7 years ago
- This TG will define AP-TEE-IO ABI extensions to provide Confidential VM-assigned devices with secure direct access to confidential memory…☆14Updated this week
- Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆33Feb 13, 2026Updated 2 weeks ago
- x86 JIT playground for documenting and exploring microarchitectural implementation details☆19Oct 15, 2025Updated 4 months ago
- oo7, a binary analysis tool to defend against Spectre vulnerabilities☆34Oct 16, 2020Updated 5 years ago
- This repository contains some tools to monitor the UNC_CBO_CACHE_LOOKUP event of the C-Boxes.☆12Oct 11, 2017Updated 8 years ago
- Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5☆30Updated this week
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆28Jun 25, 2025Updated 8 months ago
- DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-c…☆10Dec 7, 2023Updated 2 years ago