CPU-Security / Spectre-V4-ngLinks
The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Speculative Store Bypass (SSB) predictor and the Predictive Store Forwarding (PSF) predictor in AMD Zen3 Processores.
☆22Updated 2 years ago
Alternatives and similar repositories for Spectre-V4-ng
Users that are interested in Spectre-V4-ng are comparing it to the libraries listed below
Sorting:
- ☆17Updated 3 years ago
- Medusa Repository: Transynther tool and Medusa Attack☆23Updated 5 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 4 years ago
- The open-source component of Prime+Scope, published at CCS 2021☆35Updated 2 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆21Updated 4 years ago
- ☆17Updated 5 months ago
- The artifact for SecSMT paper -- Usenix Security 2022☆30Updated 3 years ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆30Updated 4 months ago
- HW interface for memory caches☆28Updated 5 years ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆62Updated 3 years ago
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆50Updated 6 years ago
- CleanupSpec (MICRO-2019)☆16Updated 5 years ago
- ☆46Updated 6 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Updated 4 years ago
- ☆117Updated 3 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- Implementation for the DIMVA'22 paper "Branch Different - Spectre Attacks on Apple Silicon"☆36Updated 3 years ago
- Microscope: Enabling Microarchitectural Replay Attacks☆20Updated 5 years ago
- ☆25Updated 2 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆73Updated 2 weeks ago
- Security Test Benchmark for Computer Architectures☆21Updated 2 months ago
- ☆20Updated 3 years ago
- Tool for testing and finding minimal eviction sets☆106Updated 4 years ago
- Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆33Updated 8 months ago
- ☆35Updated 4 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆56Updated 6 years ago
- Repository of the paper "Reproducing Spectre Attack with gem5, How To Do It Right?"☆17Updated 2 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆23Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆27Updated 5 months ago
- ☆99Updated last year