FPSG-UIUC / PandoraLinks
Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data
☆20Updated 3 years ago
Alternatives and similar repositories for Pandora
Users that are interested in Pandora are comparing it to the libraries listed below
Sorting:
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆37Updated 3 years ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆28Updated 3 months ago
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆45Updated 6 months ago
- A tool for detecting Spectre vulnerabilities through fuzzing☆45Updated 4 years ago
- HW interface for memory caches☆28Updated 5 years ago
- Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)☆24Updated last year
- ☆45Updated 6 years ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆62Updated 3 years ago
- ☆27Updated last year
- Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)☆60Updated 4 months ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆73Updated 7 months ago
- RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)☆21Updated 6 years ago
- ☆87Updated 2 years ago
- Artifact of "Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor" [USENIX Security 2024]☆63Updated last year
- Microarchitectural exploitation and other hardware attacks.☆96Updated last year
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆22Updated 3 years ago
- ☆95Updated last year
- ☆24Updated last year
- Security Test Benchmark for Computer Architectures☆21Updated last month
- Proof-of-concept implementation for the paper "Hammulator: Simulate Now - Exploit Later" (DRAMSec 2023)☆17Updated last month
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆56Updated 6 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆27Updated 4 months ago
- ☆40Updated 2 years ago
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆22Updated last month
- Collection of Spectre-type, Meltdown-type and MDS-type PoCs☆10Updated 5 years ago
- Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)☆30Updated 2 years ago
- Pre-Silicon Hardware Fuzzing Toolkit☆60Updated 2 months ago
- ☆18Updated last year
- Tests for verifying compliance of RMM implementations☆19Updated last month
- Medusa Repository: Transynther tool and Medusa Attack☆23Updated 5 years ago