FPSG-UIUC / Pandora
Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data
☆20Updated 2 years ago
Alternatives and similar repositories for Pandora:
Users that are interested in Pandora are comparing it to the libraries listed below
- Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)☆55Updated 2 years ago
- HW interface for memory caches☆26Updated 4 years ago
- ☆21Updated last year
- ☆18Updated 2 years ago
- ☆18Updated 6 years ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆35Updated 2 years ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆13Updated last week
- ☆14Updated last year
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆22Updated 3 months ago
- Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)☆23Updated 8 months ago
- ☆23Updated 10 months ago
- Proof-of-concept implementation for the paper "Hammulator: Simulate Now - Exploit Later" (DRAMSec 2023)☆13Updated last year
- Microarchitectural exploitation and other hardware attacks.☆85Updated 9 months ago
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆10Updated last week
- ☆44Updated 6 years ago
- Security Test Benchmark for Computer Architectures☆21Updated last month
- Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)☆27Updated last year
- Medusa Repository: Transynther tool and Medusa Attack☆20Updated 4 years ago
- Open source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆19Updated 2 months ago
- RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)☆21Updated 5 years ago
- Student Starter Code for Secure Hardware Design at MIT☆35Updated 7 months ago
- Artifacts for our ShowTime paper (AsiaCCS '23), including distinguishing cache hits and misses with the human eye.☆11Updated last year
- ☆81Updated last year
- ☆12Updated 3 years ago
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆25Updated last year
- Code repository for Coppelia tool☆22Updated 4 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆20Updated 2 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆19Updated 3 years ago
- ☆15Updated last year