Alternatives and similar repositories for Pandora:

Users that are interested in Pandora are comparing it to the libraries listed below

• FPSG-UIUC / augury
  Using Data Memory-Dependent Prefetchers to Leak Data at Rest
  ☆35Updated 2 years ago
• cispa / osiris
  Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)
  ☆56Updated 3 years ago
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• OleksiiOleksenko / SpecFuzz
  A tool for detecting Spectre vulnerabilities through fuzzing
  ☆35Updated 3 years ago
• riscv / riscv-memory-tagging
  Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
  ☆11Updated this week
• cispa / hammulator
  Proof-of-concept implementation for the paper "Hammulator: Simulate Now - Exploit Later" (DRAMSec 2023)
  ☆14Updated last year
• cgvwzq / cachequery
  HW interface for memory caches
  ☆26Updated 4 years ago
• compsec-snu / specdoctor
  ☆21Updated last year
• cispa / indirect-meltdown
  Proof-of-concept implementation for the paper "Indirect Meltdown: Building Novel Side-Channel Attacks from Transient Execution Attacks" (…
  ☆20Updated last year
• ahoi-attacks / WeSee
  Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)
  ☆23Updated 9 months ago
• sycuricon / MorFuzz
  Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
  ☆25Updated last year
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆11Updated 3 years ago
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 2 years ago
• miaochenlu / arch_sec_papers
  ☆14Updated last year
• scy-phy / FetchBench
  ☆15Updated last year
• CactiLab / BYOTee-Build-Your-Own-TEEs
  ☆20Updated last year
• owenlly / Indirector_Artifact
  Artifact of "Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor" [USENIX Security 2024]
  ☆60Updated 6 months ago
• sam1013 / timberv-riscv-tools
  RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
  ☆21Updated 5 years ago
• isec-tugraz / halfdouble
  ☆14Updated 2 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆20Updated 2 years ago
• amdprefetch / amd-prefetch-attacks
  ☆23Updated 11 months ago
• googleinterns / hw-fuzzing
  ☆81Updated 2 years ago
• codexlynx / hardware-attacks-state-of-the-art
  Microarchitectural exploitation and other hardware attacks.
  ☆85Updated 10 months ago
• cispa / Microarchitectural-Hash-Function-Recovery
  Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)
  ☆27Updated last year
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆15Updated last month
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆58Updated 6 months ago
• zzrcxb / LLCFeasible
  Open source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)
  ☆20Updated 3 months ago
• isec-tugraz / msrevelio
  ☆34Updated last year
• vusec / tlbdr
  ☆18Updated 2 years ago
• hw-sw-contracts / revizor
  Fuzzer that searches for vulnerabilities like Spectre and Meltdown in CPUs
  ☆42Updated 2 years ago