MATCHA-MIT / SHD-StarterCodeLinks
Student Starter Code for Secure Hardware Design at MIT
☆85Updated last year
Alternatives and similar repositories for SHD-StarterCode
Users that are interested in SHD-StarterCode are comparing it to the libraries listed below
Sorting:
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆76Updated 2 months ago
- Revizor - Hardware fuzzing for the age of speculation☆176Updated this week
- TikTag: Breaking ARM's Memory Tagging Extension with Speculative Execution (IEEE S&P 2025)☆85Updated last year
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆31Updated 6 months ago
- Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆33Updated 9 months ago
- InSpectre Gadget: in-depth inspection and exploitability analysis of Spectre disclosure gadgets☆59Updated last week
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆138Updated last year
- Source code & scripts for experimental characterization and real-system demonstration of RowPress, a widespread read disturbance phenomen…☆36Updated 2 years ago
- ☆119Updated 3 years ago
- Constantine is a compiler-based system to automatically harden programs against microarchitectural side channels☆82Updated 2 months ago
- Microarchitectural exploitation and other hardware attacks.☆95Updated last year
- Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)☆65Updated 7 months ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆62Updated 3 years ago
- Proof-of-concept implementation for the paper "CacheWarp: Software-based Fault Injection using Selective State Reset" (USENIX Security 20…☆64Updated last year
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆49Updated 8 months ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆38Updated 3 years ago
- Medusa Repository: Transynther tool and Medusa Attack☆23Updated 5 years ago
- Artifact of "Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor" [USENIX Security 2024]☆64Updated last year
- Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)☆26Updated last year
- Training in Transient Execution and PhantomCALL, from Inception (SEC'23) Artifacts.☆41Updated last year
- Tool for testing and finding minimal eviction sets☆107Updated 4 years ago
- Artefacts for: "VMScape: Exposing and Exploiting Incomplete Branch Predictor Isolation in Cloud Environments"☆33Updated 2 months ago
- ☆17Updated 3 years ago
- ☆30Updated last year
- Website and PoC collection for transient execution attacks☆200Updated last year
- ☆87Updated 2 years ago
- HW interface for memory caches☆28Updated 5 years ago
- Proof-of-concept for the GhostWrite CPU bug.☆117Updated last year
- The top repository for the code accompanying our paper "Mind the Gap: Studying the Insecurity of Provably Secure Embedded Trusted Executi…☆15Updated 3 years ago
- Pre-Silicon Hardware Fuzzing Toolkit☆60Updated 4 months ago