Alternatives and similar repositories for SHD-StarterCode

Users that are interested in SHD-StarterCode are comparing it to the libraries listed below

• vusec / inspectre-gadget
  InSpectre Gadget: in-depth inspection and exploitability analysis of Spectre disclosure gadgets
  ☆57Updated 2 weeks ago
• compsec-snu / tiktag
  TikTag: Breaking ARM's Memory Tagging Extension with Speculative Execution (IEEE S&P 2025)
  ☆85Updated last year
• microsoft / sca-fuzzer
  Revizor - a fuzzer to search for microarchitectural leaks in CPUs
  ☆166Updated 2 weeks ago
• CMU-SAFARI / RowPress
  Source code & scripts for experimental characterization and real-system demonstration of RowPress, a widespread read disturbance phenomen…
  ☆35Updated last year
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆30Updated 5 months ago
• comsec-group / cascade-artifacts
  Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
  ☆137Updated last year
• zzrcxb / LLCFeasible
  Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)
  ☆33Updated 8 months ago
• FPSG-UIUC / augury
  Using Data Memory-Dependent Prefetchers to Leak Data at Rest
  ☆38Updated 3 years ago
• cispa / CacheWarp
  Proof-of-concept implementation for the paper "CacheWarp: Software-based Fault Injection using Selective State Reset" (USENIX Security 20…
  ☆63Updated last year
• owenlly / Indirector_Artifact
  Artifact of "Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor" [USENIX Security 2024]
  ☆64Updated last year
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆23Updated 5 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆73Updated 3 weeks ago
• cispa / osiris
  Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)
  ☆61Updated 6 months ago
• vusec / tlbdr
  ☆17Updated 3 years ago
• cgvwzq / evsets
  Tool for testing and finding minimal eviction sets
  ☆106Updated 4 years ago
• comsec-group / vmscape
  Artefacts for: "VMScape: Exposing and Exploiting Incomplete Branch Predictor Isolation in Cloud Environments"
  ☆29Updated last month
• amdprefetch / amd-prefetch-attacks
  ☆29Updated last year
• cispa / GhostWrite
  Proof-of-concept for the GhostWrite CPU bug.
  ☆115Updated last year
• codexlynx / hardware-attacks-state-of-the-art
  Microarchitectural exploitation and other hardware attacks.
  ☆95Updated last year
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆62Updated 3 years ago
• comsec-group / inception
  Training in Transient Execution and PhantomCALL, from Inception (SEC'23) Artifacts.
  ☆40Updated last year
• 0xADE1A1DE / Mastik
  ☆117Updated 3 years ago
• cispa / BranchDifferent
  Implementation for the DIMVA'22 paper "Branch Different - Spectre Attacks on Apple Silicon"
  ☆36Updated 3 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆28Updated 5 years ago
• ahoi-attacks / WeSee
  Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)
  ☆25Updated last year
• pietroborrello / constantine
  Constantine is a compiler-based system to automatically harden programs against microarchitectural side channels
  ☆81Updated last month
• sycuricon / MorFuzz
  Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
  ☆46Updated 7 months ago
• isec-tugraz / halfdouble
  ☆16Updated 3 years ago
• ahoi-attacks / heckler
  Breaking Confidential VMs with Malicious Interrupts (USENIX Security 2024)
  ☆34Updated last year
• scy-phy / FetchBench
  ☆19Updated 2 years ago