skiphansen / panog2_ldr
Network based loader and flasher for Pano G2 devices
☆14Updated last year
Alternatives and similar repositories for panog2_ldr:
Users that are interested in panog2_ldr are comparing it to the libraries listed below
- Port of Brian Bennet's NES Emulator for the second generation Panologic thin client☆12Updated 2 years ago
- Prebuilt images for Linux for the Pano Logic G2☆13Updated last year
- Flashing Pano Logic thin clients without a programmer☆40Updated 2 years ago
- TI-99/4A FPGA implementation for the Icestorm toolchain☆15Updated this week
- XT-like PC written in SystemVerilog☆13Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated 2 years ago
- This is a collection of software and hardware modules for the Panologic thin client.☆12Updated last year
- Minimig project example for FleaFPGA Ohm Experimenter Board☆26Updated 2 years ago
- Programming algorithm for ATF22V10C Generic Array Logic chip.☆14Updated 6 years ago
- xinu68k: Xinu for the Motorola MECB, AT&T PC 7300, AT&T UNIX PC, AT&T/Olivetti 3B1, Convergent Technologies S/50, and Sun Microsystems Su…☆14Updated 2 years ago
- SNES SPC music player for Tang Nano 20k☆19Updated last year
- Motorola 68000 (32 bit with unneeded instructions removed) in an FPGA.☆13Updated 9 months ago
- Open-source HDMI/DVI transmitter for the Gowin GW1NSR-powered Tang Nano 4K☆24Updated 2 years ago
- sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility☆30Updated last week
- Z80 CPU + UART + Timer + I/O Ports coded in VHDL and implemented for the Lattice iCE40-hx8k dev board☆9Updated 8 years ago
- Bit streams forthe Ulx3s ECP5 device☆16Updated last year
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated last year
- DVI PMOD adapter (HDMI connector)☆28Updated 3 years ago
- Simple custom computer on a FPGA☆26Updated 10 years ago
- Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs☆28Updated 3 years ago
- Gate array reverse engineering☆21Updated 3 weeks ago
- A System Verilog/FPGA implementation of the Gigatron project.☆17Updated 6 years ago
- Smol 2-stage RISC-V processor in nMigen☆25Updated 3 years ago
- PLEASE MOVE TO PAWSv2☆17Updated 2 years ago
- A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client☆34Updated 6 years ago
- Information on cores available on the Ulx3s ECP5 FPGA board☆14Updated 4 years ago
- Code to support porting MiST cores to other boards.☆44Updated 3 weeks ago
- cpm-m3: CP/M-M3 is a port of CP/M-68K to the ARM Cortex-M3 by Roger Ivie☆15Updated 2 years ago
- A Motorola 68000 Computer☆21Updated 5 years ago
- "Designing Video Game Hardware in Verilog" in iCE40HX8K Breakout Board.☆18Updated 5 years ago