Alternatives and similar repositories for chiptools

Users that are interested in chiptools are comparing it to the libraries listed below

• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated 3 weeks ago
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 9 years ago
• pabennett / ethernet_mac
  A VHDL implementation of an Ethernet MAC
  ☆14Updated 12 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated 3 weeks ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆44Updated 9 years ago
• cambridgehackers / fpgajtag
  A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
  ☆35Updated 2 years ago
• olofk / simple_spi
  SPI core
  ☆15Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆60Updated 2 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• olofk / i2c
  I2C controller core
  ☆16Updated 2 years ago
• warclab / idea
  iDEA FPGA Soft Processor
  ☆16Updated 8 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• AnttiLukats / HackaZynq
  Open Source ZYNQ Board
  ☆31Updated 9 years ago
• rprinz08 / arty-s7-multinic
  ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface
  ☆13Updated 4 years ago
• udara28 / SDRAM_Controller
  Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
  ☆21Updated 9 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆36Updated 2 years ago
• maltevesper / JetStream-driver
  ☆14Updated 8 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆17Updated 4 years ago
• xupsh / Amp-zynq
  Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors
  ☆20Updated 9 years ago
• wd5gnr / verifla
  Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
  ☆33Updated 6 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆46Updated 4 years ago
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆24Updated 7 years ago
• hamsternz / MMCM_GPSDO
  An all-digital GPS disciplined oscillator using MMCM phase shift.
  ☆29Updated 2 years ago
• andrecp / myhdl_simple_uart
  A very simple UART implementation in MyHDL
  ☆17Updated 10 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆90Updated 5 years ago