Alternatives and similar repositories for Boot-Debian-On-Litex-Rocket

Users that are interested in Boot-Debian-On-Litex-Rocket are comparing it to the libraries listed below

• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆81Updated last month
• ldoolitt / vhd2vl
  ☆137Updated last year
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆70Updated 3 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆33Updated 9 months ago
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆30Updated 2 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆43Updated 10 months ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆92Updated 5 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 9 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• fredrequin / verilator_gowin
  Re-coded Gowin GW1N primitives for Verilator use
  ☆20Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆48Updated last week
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆58Updated 3 weeks ago
• MichaelBell / tinyQV
  A Risc-V SoC for Tiny Tapeout
  ☆43Updated last week
• wavedrom / vcd-samples
  sample VCD files
  ☆39Updated 2 months ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆92Updated 7 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆108Updated 3 weeks ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆61Updated last year
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆96Updated 5 years ago
• olofk / vidbo
  Virtual Development Board
  ☆64Updated 4 years ago
• fuad1502 / oombak
  Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!
  ☆47Updated 2 months ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆73Updated last week
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆97Updated last year
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 4 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆26Updated last month