dreylago / logicminLinks
Logic Minimization in Python
☆24Updated last year
Alternatives and similar repositories for logicmin
Users that are interested in logicmin are comparing it to the libraries listed below
Sorting:
- Integer Multiplier Generator for Verilog☆23Updated 5 months ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Updated 8 years ago
- Python EDA☆337Updated 11 months ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆47Updated last year
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Mutation Cover with Yosys (MCY)☆89Updated 2 weeks ago
- FPGA tool performance profiling☆103Updated last year
- Hardware implementation of the SipHash short-inout PRF☆17Updated 8 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 7 months ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- Provides a packaged collection of open source EDA tools☆12Updated 6 years ago
- A circuit toolkit☆106Updated 5 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Updated 7 years ago
- ☆18Updated 5 years ago
- C++ truth table library☆63Updated 4 months ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- Open-source FPGA research and prototyping framework.☆210Updated last year
- A list of VHDL codes implementing cryptographic algorithms☆27Updated 4 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆39Updated 9 months ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆26Updated 2 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Fine Grain FPGA Overlay Architecture and Tools☆28Updated 4 years ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆103Updated 10 months ago
- A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.☆165Updated 5 years ago
- ☆13Updated 4 years ago
- Libre Silicon Compiler☆22Updated 4 years ago