metr0jw / Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGALinks
Energy-efficient Event-driven Spiking Neural Network accelerator for FPGA with PyTorch integration
☆98Updated 3 weeks ago
Alternatives and similar repositories for Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA
Users that are interested in Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA are comparing it to the libraries listed below
Sorting:
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆40Updated 5 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Updated 5 years ago
- Spiking Neural Network RTL Implementation☆64Updated 4 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆215Updated 6 years ago
- A repository FPGA-friendly SNN models☆35Updated 4 years ago
- FPGA Design of a Spiking Neural Network.☆45Updated last year
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆92Updated 3 years ago
- SNN on FPGA☆11Updated 3 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Updated 10 months ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆64Updated 4 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆75Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Updated 6 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆14Updated 2 years ago
- ☆20Updated 4 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆15Updated 4 years ago
- Framework for radix encoded SNN on FPGA☆18Updated 4 years ago
- Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.☆198Updated 2 years ago
- Notebooks and code for Neuromorphic Hardware Workshop at ISFPGA 2024.☆65Updated last year
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Updated 2 years ago
- ☆53Updated last year
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆27Updated 6 years ago
- Modeling of memristors in LTSpise environment☆37Updated last month
- I will share some useful or interesting papers about neuromorphic processor☆28Updated 11 months ago
- ☆98Updated 5 years ago
- ☆17Updated 4 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆19Updated 5 years ago
- ☆44Updated 3 years ago
- SATA_Sim is an energy estimation framework for Backpropagation-Through-Time (BPTT) based Spiking Neural Networks (SNNs) training and infe…☆28Updated last year
- ☆30Updated 3 years ago