nlsynth / karutaLinks
Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
☆107Updated 3 years ago
Alternatives and similar repositories for karuta
Users that are interested in karuta are comparing it to the libraries listed below
Sorting:
- Polyphony is Python based High-Level Synthesis compiler.☆108Updated 11 months ago
- Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)☆35Updated 4 years ago
- Open source RISC-V IP core for FPGA/ASIC design☆32Updated last year
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆45Updated 4 years ago
- Binary Neural Network Framework for FPGA(Differentiable LUT)☆170Updated 5 months ago
- Original FPGA platform☆71Updated last week
- Instruction set simulator for RISC-V☆54Updated 5 years ago
- ☆54Updated last year
- (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…☆27Updated 2 years ago
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆53Updated 9 years ago
- ☆39Updated last year
- ☆14Updated 6 years ago
- RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo☆13Updated 5 years ago
- みんなのSystemVerilog☆19Updated 3 years ago
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆324Updated last year
- 10G Ethernet MAC implementation☆23Updated 5 years ago
- ☆16Updated 9 years ago
- Tiny MIPS for Terasic DE0☆36Updated 11 years ago
- Let's write RISC-V CPU in Veryl!☆57Updated last month
- FPGA Magazine No.18 - RISC-V☆18Updated 8 years ago
- Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.☆28Updated 4 years ago
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆360Updated 2 years ago
- 「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ☆10Updated 4 years ago
- ☆236Updated 2 years ago
- Basic Common Modules☆46Updated last month
- Verilog generation tool written in Rust☆62Updated 2 years ago
- ☆27Updated 2 months ago
- ☆38Updated 8 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Updated last year
- RISC-V documentation transrate to Japanese.☆73Updated 4 years ago