nlsynth / karutaLinks
Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
☆105Updated 3 years ago
Alternatives and similar repositories for karuta
Users that are interested in karuta are comparing it to the libraries listed below
Sorting:
- ☆1Updated 2 months ago
- Polyphony is Python based High-Level Synthesis compiler.☆105Updated 4 months ago
- Open source RISC-V IP core for FPGA/ASIC design☆30Updated 10 months ago
- Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)☆35Updated 3 years ago
- ☆52Updated 10 months ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆45Updated 4 years ago
- Original FPGA platform☆65Updated this week
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆52Updated 8 years ago
- ☆14Updated 5 years ago
- FPGA Magazine No.18 - RISC-V☆17Updated 7 years ago
- みんなのSystemVerilog☆19Updated 3 years ago
- RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo☆13Updated 5 years ago
- 10G Ethernet MAC implementation☆21Updated 4 years ago
- Instruction set simulator for RISC-V☆53Updated 4 years ago
- ☆14Updated 8 years ago
- Binary Neural Network Framework for FPGA(Differentiable LUT)☆158Updated 6 months ago
- Basic Common Modules☆38Updated 2 weeks ago
- Let's write RISC-V CPU in Veryl!☆44Updated this week
- Verilog generation tool written in Rust☆58Updated last year
- This is my first trial project for designing RISC-V in Chisel☆17Updated last year
- ☆38Updated 8 years ago
- ☆39Updated 9 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Meno is a tool that visualizes hierarchical data, such as the sizes of directory trees or synthesized circuit sizes. It can be built into…☆12Updated last month
- Tiny MIPS for Terasic DE0☆35Updated 11 years ago
- RISC-V documentation transrate to Japanese.☆73Updated 3 years ago
- (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…☆21Updated 2 years ago
- An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019☆17Updated 4 years ago
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆319Updated 9 months ago
- Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.☆28Updated 4 years ago