zhaijw18 / mcpat-calib-public
A RISC-V BOOM Microarchitecture Power Modeling Framework
☆24Updated last year
Alternatives and similar repositories for mcpat-calib-public:
Users that are interested in mcpat-calib-public are comparing it to the libraries listed below
- The open-sourced version of BOOM-Explorer☆38Updated last year
- An integrated CGRA design framework☆87Updated 4 months ago
- A list of our chiplet simulaters☆31Updated 3 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- ☆29Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆18Updated 10 months ago
- An Open-Source Tool for CGRA Accelerators☆59Updated 2 months ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆15Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated last month
- Dataset for ML-guided Accelerator Design☆36Updated 4 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated last week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆46Updated 5 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 8 months ago
- ☆23Updated 7 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆48Updated last week
- DRA+RISC-V Exploration Framework☆16Updated last year
- ☆47Updated last month
- ☆42Updated this week
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆53Updated last month
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆43Updated 6 months ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆64Updated this week
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆146Updated 5 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 5 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆44Updated 10 months ago
- gem5 repository to study chiplet-based systems☆70Updated 5 years ago