zhaijw18 / mcpat-calib-publicLinks
A RISC-V BOOM Microarchitecture Power Modeling Framework
☆24Updated 2 years ago
Alternatives and similar repositories for mcpat-calib-public
Users that are interested in mcpat-calib-public are comparing it to the libraries listed below
Sorting:
- An Open-Source Tool for CGRA Accelerators☆67Updated 2 months ago
- The open-sourced version of BOOM-Explorer☆40Updated 2 years ago
- ☆33Updated 3 weeks ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆16Updated last year
- A list of our chiplet simulaters☆33Updated 2 months ago
- An integrated CGRA design framework☆89Updated 3 months ago
- DRA+RISC-V Exploration Framework☆16Updated last year
- An Open-Source Tool for CGRA Accelerators☆21Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- ☆45Updated 3 weeks ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆132Updated last week
- RTL generator for SpGEMM☆12Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- ☆55Updated 3 months ago
- gem5 repository to study chiplet-based systems☆75Updated 6 years ago
- ☆34Updated 6 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆57Updated 3 months ago
- RTL implementation of Flex-DPE.☆103Updated 5 years ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆68Updated 2 weeks ago
- ☆17Updated last month
- Dataset for ML-guided Accelerator Design☆37Updated 7 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆68Updated 3 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆18Updated 2 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 3 weeks ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆81Updated last month
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- ☆29Updated last month